By Senior Associate Editor Samuel K. Moore

Samuel K. Moore

Look at any modern microprocessor, and you'll see that most of the chip bares the telltale coppery sheen of embedded memory. Right now, that memory is mostly SRAM, but a rival technology is gaining ground. Two recent develops in embedded DRAM, which is much more dense but a little slower and harder to construct, show that chipmakers are increasingly desperate to pack tons of memory onto their chips without making them much bigger and therefore more costly. Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) said on 6 March that it made the first functional 65-nanometer chip with embedded DRAM, a graphics chip for NVIDIA Corp. containing multiple megabytes of memory. And last month, IBM presented a new embedded DRAM technology.

TSMC says its 65-nm embedded DRAM has a higher bandwidth, consumes less lower power, and the bit-storing cells are nearly half the size of the previous generation. TSMC's been moving fast, putting out its first embedded DRAM-dependent chip of the previous generation, 90 nm, around this time last year and moving to 65 nm only in the second quarter of 2006.

Sreedhar Natarajan, president of Emerging Memory Technologies, in Kanata, Ontario, who has worked on TSMC 65-nm eDRAM designs told IEEE Spectrum that the TSMC technology should be a good fit for chips used in mobile consumer products. Indeed, NVIDIA hinted that cellphones were the target of its new chip. "The efficiencies of the embedded DRAM process allowed us to raise the bar for features found in mainstream cellphones," Michael Rayfield, general manager of the handheld division of NVIDIA, said in a statement.

Low power consumption is the key to getting chips into mobile gadgets. TSMC says its new memory includes power-saving options such as sleep mode, partial power cut-off, and technology to keep the chip's temperature steady.

DRAM's advantage over other memory types is that it is dense. A cell consists of a single transistor and capacitor, compared to an SRAM cell, which requires six transistors. The bit is stored as charge in the capacitor and the transistor acts as the bit's gatekeeper. Although the transistor can shrink from generation to generation, following Moore's Law, the capacitor must stay comparatively large. So most standalone DRAM is made by digging a deep, narrow trench beside each transistor. TSMC instead builds the capacitor—two layers of metal sandwiching an insulator—above the transistor, in the layers of insulation that usually hold the wiring that links transistors together. Other companies, such as Innovative Silicon, eliminate the capacitor entirely by using a layer of insulation buried within a certain type of silicon wafer, called silicon-on-insulator (SOI).

In February, IBM presented its own 65-nm embedded DRAM technology using SOI. Like standalone DRAM built on regular silicon, it's capacitor resides in a trench beside the transistor, but IBM makes use of SOI's insulation to reduce the number of processing steps needed to make the memory cells. The company says the technology is expected to be a key feature of its next-generation, 45-nm offerings and will be available in 2008. AMD was a development partner on the technology, but it has also been working with Innovative Silicon's technology (see January's "Winner: Masters of Memory").

Semico Research's Bob Merritt sees the IBM development as a big shift in how chipmakers value their on-chip memory. "The performance of the memory is such a critical element in the processor's overall performance that the efficiency of the memory can become the primary consideration in selecting the manufacturing process for the microprocessor!" he wrote in a 1 March blog.


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