7 December 2011—After years of doping, straining, shrinking, and tweaking, engineers seem to have exhausted all their strategies for improving the planar complementary metal-oxide semiconductor (CMOS) transistors at the heart of today’s computer processors. Producers of cutting-edge chips are now resorting to new structures—building up in three dimensions or constructing transistors in ultrathin layers of silicon—to ensure that devices keep shrinking and that Moore’s Law keeps going just a bit longer.
But semiconductor start-up SuVolta is betting that the traditional planar structure still has some life in it and that it can go toe-to-toe with the new alternative designs. The firm hopes to build a business licensing a technology it says will reduce power consumption and boost performance with minimal changes to the way transistors are made.
When the Los Gatos, Calif.–based company emerged from stealth mode in June, it gave few details on exactly how this could be accomplished. But the firm is now ready to unveil the basics of the approach this week at the 2011 IEEE International Electron Devices Meeting, in Washington, D.C.
The trouble with planar transistors is twofold: When you try to make them smaller, they leak current and waste power. Just as troubling is that the more you shrink them, the harder it gets to make them uniform enough for one transistor to behave the same as the next.
To some extent, both problems are caused by unavoidable variations in the number of dopant atoms in the silicon. Silicon is traditionally doped with elements like boron or phosphorus in order to create and fine-tune the energy barriers that both block and permit current to flow. Electric fields are used to steer streams of dopants into the silicon.
But as chipmakers have reduced the size of CMOS transistors, the total number of dopant atoms in a key part of the transistor, the channel, gets smaller. The channel is used to carry current between the source and the drain, and it’s controlled by a gate that is typically mounted on top of the channel. The fewer dopants there are, the stronger the influence of random fluctuations in the dopant concentration. These fluctuations have come to have a strong impact on a transistor’s electronic properties, resulting in a high proportion of less-than-ideal transistors that leak more power or switch slower than designed.
SuVolta hopes to make transistors less leaky and more predictable by changing the way their channel regions are doped. Instead of evenly doping a transistor channel, the company’s strategy is to lay down the channel in three layers, each about 50 to 100 angstroms thick, and each with a different concentration of dopant.
Under the influence of the gate’s voltage, current moves primarily through the topmost layer of silicon, which contains no dopants at all. The bottom layer in SuVolta’s transistor is made up of heavily doped silicon, which provides a reservoir of dopant atoms. The reservoir shields the electric field induced by the transistor gate, preventing it from penetrating deeper into the silicon, where it could create a path for current to leak across.
In between the undoped and heavily doped layers of the channel, SuVolta’s design calls for a layer with an intermediate concentration of dopants. By altering the concentration of dopants in this middle layer, SuVolta can fine-tune a transistor’s threshold voltage—the amount of voltage at the gate needed to turn the transistor on or off.
The start-up’s devices, called Deeply Depleted Channel (DDC) transistors, are a new spin on an idea from the 1990s for varying dopant concentration with depth, known as steep retrograde doping. SuVolta’s scheme involves more-abrupt jumps in dopant concentration than in the original concept and for precise layer thicknesses that vary by no more than a few atoms.
Achieving that sort of precision is something that has been possible only in the past five years or so, says SuVolta’s chief technology officer, Scott Thompson, in part because of the development of precise “blanket epitaxial” tools used to grow silicon layers. Early versions of these tools were instrumental in extending the life of planar CMOS transistors in the early 2000s by allowing chipmakers to add material to the source and drain regions of a transistor to strain the crystal structure of the transistor channel region, allowing current to flow faster.
SuVolta says that 65-nanometer transistors (the cutting-edge size in 2006) made with their technique boast half the variation in threshold voltage of ordinary CMOS transistors and leak just 20 percent as much power. “That’s actually a very, very impressive number,” says Seok-Hee Lee, an electrical engineering professor at the Korea Advanced Institute of Science and Technology in Daejeon, South Korea, who formerly worked on process integration at Intel.
Lee, who was not involved in SuVolta’s development, notes that both alternative transistor designs—3-D and ultrathin-body silicon-on-insulator (SOI) devices—present hurdles for chipmakers. Although the 3-D Tri-Gate transistors that Intel debuted in May of this year show big gains in power consumption, other chipmakers will need to devote significant resources to switch over to the new architecture and must cope with new complexities in chip design. For instance, the dimensions of these 3-D transistors (broadly known as FinFETs) are relatively fixed, limiting how much they can be fine-tuned for different applications. Although ultrathin-body SOI transistors are planar structures, they must be built on special, more-expensive wafers.
SuVolta’s approach could offer a third way. “I think this will extend the planar transistor architecture,” Lee says. “They’re achieving a similar result using bulk silicon, not the expensive SOI wafer, and the process is much simpler than FinFET architecture.”
“From a technical standpoint, it’s a solid approach,” says Tsu-Jae King Liu, a professor of electrical engineering and computer sciences at the University of California, Berkeley, and a coinventor of both the FinFET and the ultrathin-body SOI transistor.
But, Liu adds, it remains to be seen exactly how well SuVolta’s strategy will compete against FinFETs and ultrathin-body transistors. That will depend on how well the company can control the sharpness of the boundaries between differently doped layers, she says. High-temperature steps during wafer fabrication can make dopant atoms migrate, smearing out the sharp transitions between dopant layers. The pattern of migration varies from transistor to transistor and will have a bigger impact as transistors are scaled down. SuVolta’s ability to limit that migration “will determine how far their technology can go in terms of Moore’s Law,” Liu says.
SuVolta has marketed its DDC transistors as an alternative to FinFETs and ultrathin-body SOI architectures, and Thompson says the company believes it can scale the devices down so that their smallest features are just 14 nm. But he says these devices will likely make more of an impact for semiconductor companies with transistors whose smallest features are between 20 and 30 nm—the size range that’s state of the art in the chip industry today.
Thompson suspects the difficulty and cost of the advanced lithography needed to make features smaller than 20 nm will keep the industry in that range. “I think what people are going to do, though they’re not going to admit it, is they’re going to make 28 nm cheaper and lower power.” That could be a boon, particularly for processors in smartphones and tablets, he says. “The next 10 years, there’s still going to be a lot of progress from Silicon Valley. It just won’t come from making things smaller.”
Still, the jump from 65-nm technology—which SuVolta has licensed to Fujitsu—and 20 nm is a big one, and so far, SuVolta has released little data on how well its devices fare at the smallest transistor sizes. Simon Yang, an independent consultant based in Shanghai and Portland, Ore., who has been briefed by SuVolta on the technology, says he’s waiting on more data. “But I think it could potentially be a very big thing,” he says.
This article appeared in January 2012 print as "A Flat Transistor Comeback?."
This article was updated on 20 December 2011.