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Imec Demonstrates Magnetic Memory With Superfast Switching Speeds

Imec creates the first spin-orbit torque MRAM on a silicon wafer

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Micrograph that shows a SOT-MRAM unit created on a standard 300mm silicon wafer.
Image: imec

Researchers at imec in Leuven, Belgium, have completed the first demonstration of a new type of magnetic memory technology that can switch faster with less power than its predecessors.

Specifically, they showed the fabrication of spin-orbit torque magnetic random-access memory (SOT-MRAM) on a standard 300-mm silicon wafer. They made the announcement last Wednesday at the 2018 Symposia on VLSI Technology and Circuits in Honolulu.

Using a CMOS compatible process, the researchers created SOT-MRAM devices that functioned as well or even better than lab devices, bringing it closer to a technology that would replace the non-volatile and energy-consuming SRAM and DRAM currently used in computers.

SOT-MRAM is the latest development in magnetic random-access memories (MRAMs). The technology, which stores bits as a specific orientation of a magnetic field in a ferromagnetic material instead of an electric charge in a tiny capacitor, was first developed in the 1980s.

The advantage of this approach is two-fold: the memory is not volatile, which means you don't have to refresh it continuously (as is the case for data stored as charges in tiny capacitors) and the information remains preserved, even if the power is switched off. The second advantage is “endurance,“ meaning data can be written and read out a huge number of times, without degradation of the device.

The first MRAMs consisted of two ferromagnetic layers separated by a thin non-magnetic insulator, called the magnetic junction. One layer contains a fixed magnetic field that points, for example, from the left to right. The magnetic field in the other layer, the free layer, can be switched from the left to the right and back.

When the magnetization in the two ferromagnetic layers points in the same direction, the magnetic junction will allow the passage of a current from the free layer to the fixed layer, indicating the storage of a bit, or a "1." However, if the magnetic field in the free layer is changed to the opposite direction, a current between the two magnetic layers will be blocked, indicating a "0."  

Reading out the data stored in such devices, essentially a resistance measurement, was not a problem. However, writing to the device by switching the orientation of the magnetic field, was more difficult. The field could be switched by sending a current through a conductor passing close to the free layer. Because the current had to be quite strong to create an electric field that could switch around the magnetic field, these MRAMs were power hungry and found limited applications.

The spin-torque transfer MRAM (SST-MRAM) was an improvement in terms of power consumption. Instead of an external current, it uses a current passing through the device perpendicularly to the non-magnetic layer to switch the magnetic field in the free layer. While this reduced the power consumption of the device, it has the inconvenience that the write current and the read current use the same path through the device, making it prone to errors.

More recently, researchers at SPINTEC, in Grenoble and researchers at ICN2 in Barcelona, proposed a different approach that circumvents this problem. There was another way to switch the free magnetic layer, using the little-known spin-orbit torque (SOT) effect.   They found that by inserting an additional conducting heavy metal SOT layer parallel to the free ferromagnetic layer, they could switch the magnetic field in that layer by passing a current through this SOT layer.

The switching speed of the SOT-MRAM reached 210 picoseconds while the STT-MRAM, created on the same wafer, clocked a speed of 5 nanoseconds.

The device, called spin-orbit torque MRAM (SOT-MRAM), because of the separation of the write and read channels, is expected to operate at a higher speed than SST devices.

“This is an entirely new concept, a three-terminal device, and as the concept was demonstrated, we needed a manufacturing solution,” says Gouri Sankar Kar, program director at imec. His team found that the switching speed of the SOT-MRAM reached 210 picoseconds while the STT-MRAM, created on the same wafer, clocked a speed of 5 nanoseconds.

However, there are still problems that need to be solved before the device can be integrated and replace cache memory and DRAM in computers, says Kar. He mentions two: “You need some amount of magnetic field to seed the device; ideally you wouldn’t need to apply an external field,” he says, adding that they are now close to solving this problem.

The second hurdle is something that has been plaguing magnetic memories since their inception: “The current for switching the device is still too high, the problem is very complex to access, and this will take some time. It is the biggest challenge,” says Kar.

For Guillaume Prenat, a researcher at CEA, the clean-room success at imec is important for the entire spintronics research community. “The news from imec’s clean-room achievement is very important because this will allow people to try out this new technology,” he says.

He is less worried about the possible manufacturing cost of this device using CMOS technology. “Magnetic techniques generally require more masking levels than CMOS. Manufacturing the device is expensive now because the technology is not ready yet,” he says.

Editor’s note: This post was updated on 2 July 2018.

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