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Solid-State Circuits, in 3-D!

At this year's IEEE ISSCC, some 3-D integration technologies are ready to wear, while others will remain haute couture

3 min read

9 February 2009—Chipmakers are officially headed into the third dimension, as demonstrated at this week’s IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco. For a number of years, researchers have been looking for ways to stack chips vertically to reduce communication delays through lengthy wiring. ”Three-D is an important topic this year,” says Infineon’s Werner Weber, a member of the ISSCC technology directions subcommittee. Of course, there has been activity in 3-D for at least the past two years. But what’s different this year is the presentation of a chip that’s actually on the market.

Chip firms this week are reporting progress in 3-D integration for all types of memory—dynamic random-access memory (DRAM), static random-access memory (SRAM), and NAND flash—as well as in image sensors and wireless pressure sensors. The star of the 3-D integration show, however, is Toshiba Corp., according to Weber, because its chip-scale camera module is already available.

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The Transistor at 75

The past, present, and future of the modern world’s most important invention

2 min read
A photo of a birthday cake with 75 written on it.
Lisa Sheehan

Seventy-five years is a long time. It’s so long that most of us don’t remember a time before the transistor, and long enough for many engineers to have devoted entire careers to its use and development. In honor of this most important of technological achievements, this issue’s package of articles explores the transistor’s historical journey and potential future.

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