Sensor Tells Wafers When to Get Out of the Shower

Uses electrical impedance to tell when semiconductor rinse cycle should end

1 min read
Sensor Tells Wafers When to Get Out of the Shower

IEEE Spectrum’s June special report on the water-energy nexus reminds us of how little we know about how much clean water is required to enjoy the comforts of the modern age. A single chip making facility can easily consume 10 million liters of fresh water each day—close to the daily requirement of a city with 50 000 residents. But do chip fabs have to use so much of this precious resource?

A startup created by University of Arizona researchers to further develop and market technology that promises to dramatically cut water use by chipmakers recently announced that it is looking to sell its patents. Tucson based Environmental Metrology produces sensor equipment and software that detects, based on changes in electrical impedance, when a silicon wafer has been rinsed clean. Without the sensors, chip makers simply err on the side of caution, knowing that any contaminants left behind on the wafers’ surfaces will lower yields.

The technology’s developers, who claim that it can cut water use in a fab by up to 50 percent, say that companies such as AMD, Intel, Freescale, Hewlett-Packard, IBM, and Texas Instruments have expressed interest. Cutting their water use allows these tech firms to tout their social responsibility bona fides and helps their bottom lines by decreasing the amount of wastewater that they have to process to keep from running afoul of environmental laws.

 

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper
Green

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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