When a neutron, alpha particle, or some other ionizing particle strikes a solid-state memory chip, it can do a good deal of mischief by changing the data stored in a memory cell. Stray ionizing particles can come from cosmic radiation or from minuscule amounts of radioactive impurities in the material used to make the chip. Their random appearance can lead to system malfunction or even failure if critical erroneous data or instructions are sent to the processor. But such events never do permanent damage to the memory: when new data is written into the same cell, it will work just fine. For this reason, errors caused by ionizing particles are called "soft."
Fifteen years ago, soft errors emerged as a problem for dynamic RAMs, which store data in a single capacitor. But static RAMs, which store data in more complicated and sturdy six-transistor cells, were not especially vulnerable. However, as transistors have become smaller and smaller, soft errors have become a concern even for SRAMs.
The main way of coping with soft errors has been error detection and correction circuitry, a technique that adds extra memory cells to each row in the memory. Naturally, these extra cells increase the memory's manufacturing cost and power consumption. But scientists at the central R and D site of STMicroelectronics in Crolles, France, have now developed a process for greatly increasing the immunity of memory cells to ionizing particles without significant added cost or loss of memory speed.
When a neutron, proton, alpha particle--which is a helium nucleus--or other small energetic particle strikes a silicon chip, it creates electrons and holes along its path. (A hole is a missing electron in the valence band that behaves in semiconductors like an electron with a positive charge.) These positive and negative charges are scooped up by a nearby memory cell. If it collects enough charge, the data in the cell will change from a one to a zero or vice versa.
The sensitivity of memory cells to soft errors is directly related to the cell's capacitance: the smaller the capacitance, the greater the sensitivity. In concept, the approach taken by the STMicroelectronics scientists is a simple one. It is to add two extra capacitors to each memory cell. Today's SRAM cells have a capacitance of less than 3 femtofarads, which makes them very susceptible to soft errors, says Jean-Pierre Schoellkopf, director of advanced design and tools at the company's central R and D site. Since each of the extra STM capacitors--one on each side of the cell--has a value of about 35 fF, much larger than that of the cell, it is made practically immune to soft errors. Previous attempts to increase the capacitance of SRAM cells had added only about 5 fF, not enough to prevent soft errors, says Schoellkopf.
The practical difficulty in adding capacitors to a memory cell is finding a way to do it without increasing the size of the cell, which would drive up manufacturing costs. The STM researchers put the capacitors on top of the transistors that make up the cell [see micrograph, " High-Rise Memory Cell"]. To do this, they borrowed manufacturing steps from the company's embedded DRAM process, which also stacks capacitors on top of transistors.
To test their SRAM, the researchers exposed it to ionizing radiation. They found that it was completely immune to soft errors caused by alpha particles and, when biased at 1.2 V, 250 times less sensitive than conventional SRAMs to soft errors from neutrons--a rate acceptable to the semiconductor industry. The memory should be robust enough for space applications, says Philippe Roche, the company's expert in radiation effects on semiconductors. At press time, the researchers were planning tests at the Brookhaven National Laboratory in New York in which the chip will be exposed to heavy ions, the most common type of cosmic particle, to make sure it can stand the rigors of outer space.