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RF-Only Logic Makes RFID Tags Tinier

New kind of power supply for RFID and IoT logic circuits could eliminate a sizable chunk of circuitry

3 min read
An RFID chip using RF-only logic lacks a rectifier and its associated circuitry.
An RFID chip using RF-only logic lacks a rectifier and its associated circuitry.
Image: North Carolina State University

Engineers at North Carolina State University have applied a new technology called RF-only logic to create passive RFID tags that are 25 percent smaller than today’s. And a smaller tag means a cheaper tag.

The space savings comes from eliminating a circuit usually considered crucial to the chip’s operation—the rectifier. Passive RFID tags, the most common ones, are powered by an RF signal provided by the tag reader when it’s nearby. The RFID’s rectifier takes the AC radio signal and turns it into DC for use by the chip’s logic circuits. The innovation was to develop a set of circuit techniques that eliminate the need for the rectifier, allowing the logic to run directly from the oscillating radio signal.

“By eliminating the hardware that is used to convert the AC signal to DC for powering the circuit, we are able to make the RFID tag much smaller and less expensive,” says Paul Franzon, a professor of electrical and computer engineering at NC State. He presented the RF-only RFID chip earlier this month at the IEEE RFID 2016 conference in Orlando.

A typical RFID rectifier consists of a set of diodes and a capacitor. Connected to the incoming RF signal, the diodes direct only the positive part of the wave through, and the capacitor smooths out the period between the peaks. This setup typically takes 25 percent or more of the RFID chip area and adds cost and complexity, says Franzon.

He and his students replaced it with a pair of transistors for each logic circuit. The assemblage basically supplies electricity to the logic during half the radio wave, and then—relying in part on the capacitance of the next logic circuit—prevents it from leaking away during the other half.

imgThe RF-only version of an inverter is made up of two power supply transistors and two logic transistors. The capacitor represents the capacitance of the next logic gate. During half the RF signal’s cycle the power supply to the core logic is stronly on. During the other half the logic is isolated.Image: Paul Franzon, North Carolina State University

“So what we’re kind of doing is distributing the rectifier,” says Franzon.

Because it’s only on for half the cycle, it takes several cycles of radio waves for a logic circuit to make a transition, say from 0 to 1. But that’s not really a problem. “Every RF cycle you do a little more of the transition,” he says.

To further slim the circuitry, Franzon and his students developed a design algorithm that lets logic circuits share these supply transistors when possible.

His team had to solve several other design challenges to make its RF-only logic tag. For one, they had to make the power supply work both when the RFID reader is close to the tag and providing a strong signal and when it’s farther away and giving a weaker signal. For another, they needed to design a data retention flip-flop to bridge the 1.5 microseconds when the RFID protocol requires that the reader not provide power.

The RF-only technique provides a full compliment of logic, and he and his team are looking for other Internet-of-Things applications it can conquer, says Franzon. His team has even designed an RF-only analog-to-digital converter, though it played no part in the RFID project.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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