Putting Germanium in a Vise

Silicon chips with compressed germanium run faster

3 min read

24 February 2005--The old-fashioned way to speed up circuits was to shrink the components, but now that the payoff from that strategy is declining, semiconductor manufacturers are seeking other ways to squeeze out performance--notably by squeezing the semiconductor itself. If you squash or stretch certain semiconducting crystals, they convey electrical charges faster. In a CMOS transistor, the result of such "strain" is faster switching and higher current output, with most of the effect coming in the channel--the connection between the transistor's source and the drain. In the past two years, strained-silicon channels, in which the silicon is stretched, have come into general production. Now scientists at IBM Corp. have demonstrated still greater improvements in channels made of germanium that has been squeezed, or compressively strained.

According to Huiling Shang, a research staff member at the IBM Thomas J. Watson Research Center in Yorktown Heights, N.Y., transistors with strained-silicon channels offer output current just 10 to 30 percent higher than that in unstrained silicon, whereas strained-germanium channels raise it by 200 percent. She notes that although the idea had been kicking around for a few years, it became practical only when IBM discovered a fabrication method compatible with conventional CMOS technology, the linchpin of the electronics industry. The company announced the discovery in December, at the International Electron Devices Meeting, in San Francisco.

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper
Green

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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