Printing III-V Transistors Onto Silicon

Engineers use a rubber stamp to get silicon and compound semiconductors to cooperate

2 min read

11 November 2010—Researchers have been trying for years to grow circuits made from compound semiconductors—known for their high frequency and light-emitting capabilities—on silicon with little success. The techniques were complicated and often resulted in defects. Even under the best circumstances, the resulting transistors were plagued by current leakage at the junctures where the two types of material met, which reduced the transistors’ efficiency. But a group of researchers in the United States and Taiwan, reported this week in Nature that they have hit upon a relatively simple way to integrate compound semiconductors and silicon with none of these drawbacks.

The team created high-performance nanometer-scale transistors using a pick-and-place printing process that puts indium arsenide nanoribbons on a silicon–silicon dioxide substrate in a way that is likely to deliver high yields and throughput. Though the technique itself isn’t new, this is the first time it has been shown to reliably print working nanometer-scale compound semiconductor devices on silicon.

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Emily Cooper
Green

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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{"imageShortcodeIds":[]}