On-Chip Supercapacitors Dump Carbon in Favor of Silicon

For the first time a silicon-based material competes with carbon- and graphene-based solutions in supercapacitor electrodes

2 min read
On-Chip Supercapacitors Dump Carbon in Favor of Silicon
Images: VTT

Tiny supercapacitors that can fit right on a chip have been hotly pursued for at least the last half decade. We’ve seen the usual suspects—graphene, titanium carbide and porous carbon—proposed for making the electrode material for these on-chip supercapacitors.

Now researchers at the VTT Technical Research Centre of Finland have turned to an unlikely material for producing these pint-sized energy storage devices: porous silicon.  What have the researchers done to turn this notoriously weak electrode material into a powerhouse? They have found that topcoating it with a nanometer-thick layer of titanium nitride makes all the difference.

“Porous silicon without a coating is an extremely poor supercapacitor electrode material,” explained Mika Prunnila, Research Team Leader at VTT, in an email interview with IEEE Spectrum. “The main problems are chemical reactivity and high electrical resistivity. The chemical reactiveness leads to poor stability. The high resistivity leads to low power.”

Prunnila notes that that adding high concentrations of dopants doesn’t help much. Highly doped porous silicon can still behave as a good insulator because the size of the small nanostructures leads to strong depletion in the remaining silicon.

The thin layer of titanium nitride solves both problems, either of which would be showstoppers, says Prunnila. “It provides chemical inertness and high conductivity leading to high stability and high power, respectively. At the same time porous silicon provides the high surface area matrix.”

The performance figures reported by Prunnila and his colleagues in a paper published in the journal Nano Energy are impressive. While the researchers reported achieving up to 13,000 charge-discharge cycles without significant deterioration in capacitance, Prunnila told IEEE Spectrum that they have continued to charge it up and deplete it; thus far, they’ve gone through upwards of 50,000 cycles (even letting the electrodes dry in the middle of the cycling) without physical or electrical deterioration.

“[The number we reported in the paper was] limited by the available measurement time, not by the performance of the electrodes,” says Prunilla. “I’d say that supercapacitors ‘must’ be stable up to 100,000 cycles, and as [this device’s] capacitance is fully stable up to 50,000 porous Si-TiN electrodes pass the test.”

As far as the power density and energy density of the supercapacitors, the devices the VTT team has developed compare favorably with state-of-the-art. In the paper, the researchers point to existing on-chip microcapacitor devices made from graphene oxide/reduced graphene oxide (GO/RGO) with a power density of 200 watts per cubic centimeter and an energy density of 2 milliwatt-hours per cubic centimeter. The devices the VTT researchers have developed have power densities of up to 214 W/cm3 and energy densities of 1.3 mWh/cm3. These numbers mark the first time that a silicon-based material has reached par with carbon- and graphene-based solutions in these metrics, according to Prunilla.

The engineering challenge remains in packaging. Also, there remains the need to increase the capacitance level per unit surface area in order to reach the maximal level that the technology promises.

“Such a capacitor has many potential use cases, from stabilizing the power of consumer electronic devices to local energy storage of energy harvesters,” says Prunilla.

In continuing research, the VTT scientists are performing further material and device studies aimed at optimizing the supercapacitor electrodes. “Here, one important topic is to increase the fundamental understanding of the electrical and electrochemical behavior of the titanium nitride electrolyte interface,” added Prunilla.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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