Researchers at IBM believe the future of the transistor is in stacked nanosheets. After a decade of research, most recently in partnership with Samsung and Global Foundries, the company will describe 5-nanometer node test chips based on these transistors today at the Symposium on VLSI Technology and Circuits in Kyoto.
Today’s state-of-the-art transistor is the finFET, named for the fin-like ridges of current-carrying silicon that project from the chip’s surface. The silicon fins are surrounded on their three exposed sides by a structure called the gate. The gate switches the flow of current on, and prevents electrons from leaking out when the transistor is off. This design is expected to last from this year’s bleeding-edge process technology, the “10-nanometer” node, through the next node, 7 nanometers. But any smaller, and these transistors will become difficult to switch off: electrons will leak out, even with the three-sided gates.
So the semiconductor industry has been working on alternatives for the upcoming 5 nanometer node. One popular idea is to use lateral silicon nanowires that are completely surrounded by the gate, preventing electron leaks and saving power. This design is called “gate all around.” IBM’s new design is a variation on this. In their test chips, each transistor is made up of three stacked horizontal sheets of silicon, each only a few nanometers thick and completely surrounded by a gate.
Why a sheet instead of a wire? Huiming Bu, director of silicon integration and devices at IBM, says nanosheets can bring back one of the benefits of pre-finFET, planar designs. Designers used to be able to vary the width of a transistor to prioritize fast operations or energy efficiency. Varying the amount of silicon in a finFET transistor is not practicable because it would mean making some fins taller and other shorter. Fins must all be the same height due to manufacturing constraints, says Bu.
IBM’s nanosheets can range from 8 to 50 nanometers in width. “Wider gives you better performance but takes more power, smaller width relaxes performance but reduces power use,” says Bu. This will allow circuit designers to pick and choose what they need, whether they are making a power efficient mobile chip processor or designing a bank of SRAM memory. “We are bringing flexibility back to the designers,” he says.
The test chips have 30 billion transistors. The company has not benchmarked them against 7 nanometer designs, since those are not on the market. Compared to 10 nanometer chips, the new designs have a 40 percent performance enhancement at a given power; at matched performance, they can save 75 percent on power.
Mukesh Khare, vice president of semiconductor technology and research at IBM, says that the company has spent years working on the process technology and materials for making stacked nanosheets.
The research chips were made using electron-beam lithography—a technology too expensive for mass production. But by the time 5-nanometer chips go into production extreme-ultraviolet lithography (EUV) will be available to reduce costs, according to Khare. He says that it takes the same number of EUV lithography masks—the patterns to be projected onto to the chip to form transistor components—to make a 5-nanometer nanosheet transistor as it does to make an equivalent finFET.
IBM plans to offer this technology to their customers at the 5-nanometer node. “We think this will become the prevalent structure beyond finFET,” says Khare.
Katherine Bourzac is a freelance journalist based in San Francisco, Calif. She writes about materials science, nanotechnology, energy, computing, and medicine—and about how all these fields overlap. Bourzac is a contributing editor at Technology Review and a contributor at Chemical & Engineering News; her work can also be found in Nature and Scientific American. She serves on the board of the Northern California chapter of the Society of Professional Journalists.