Nano-ink Research Gives New Life to Painted-on Solar Power Conversion

Making solar power conversion cheap rather than efficient is the aim of recent nanoparticle ink research

2 min read
Nano-ink Research Gives New Life to Painted-on Solar Power Conversion

The perpetual balancing act between cost and efficiency that seems inherent in photovoltaics marches on.

We see this exhibited in among other things the “Photovoltaic Moore’s Law”, which is based on ever decreasing price points rather than the ever increasing number of transistors per unit of a chip—lowering price rather than heightening technology. But efficiencies still need to be improved for photovoltaics. So how do you improve the efficiency of a photovoltaic for turning sunlight into electricity when you’re overriding concern is to make the whole thing cheaper?

Recently, when it was argued that Multiexciton Generation, a process by which several charge carriers (electrons and holes) are generated from one photon, might not be as promising an avenue as had been hoped, the possibilities for thin film solar cells becoming more efficient took a fairly serious blow.

So, maybe the way to go is one that was presented to me in the comments to the blog entry cited at the top of this one: “When it comes to improving market penetration for solar power (which, after all, is what we are concerned with if we want to reduce fossil fuel use), you can't beat McDonalds for a business model. Make 'em cheap, make 'em fast, make 'em consistent, and have 'em ready when I'm hungry.”

Along these lines, researchers at the University of Texas have conducted research into using nanoparticle inks that would replace the standard solar cell manufacturing process. 


The research, which was originally published in the ACS journal The Journal of Physical Chemistry
, could usher in that long-promised application of painting solar power onto a building.

However, at present spray-on nanoparticle inks for solar power are only 1% efficient. This will need to be improved, according to Brian Korgel, one of the researchers at the University of Texas.

“If we get to 10 percent, then there’s real potential for commercialization,” Korgel said. “If it works, I think you could see it being used in three to five years.”

It also appears that commercialization is at the forefront of the University of Texas’ plans as a partnership with Konarka Technologies was announced in January.

While three to five years may sound reasonable to a researcher who believes in their work, maybe the folks at Konarka can educate that researcher into the difficulties of getting a product to market no matter how promising the technology and the particularly difficult road for organic photovoltaics.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD

A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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