Once you’ve gone from 2-D to 3-D, the next logical step is 4-D, right? Well at least that's the progression that researchers at Purdue and Harvard University want to make. The joint research team has developed a transistor consisting of three nanowires made out of indium-gallium-arsenide instead of silicon. The resulting transistor’s combination of speed and stacking capabilities have led the researchers to refer to it as ‘4-D’.
“It's a preview of things to come in the semiconductor industry," said Peide "Peter" Ye, a professor of electrical and computer engineering at Purdue University, in a press release. "A one-story house can hold so many people, but more floors, more people, and it's the same thing with transistors. Stacking them results in more current and much faster operation for high-speed computing. This adds a whole new dimension, so I call them 4-D."
The advance couldn't be more timely, at least insofar as the transistor is shaped a bit like a Christmas tree—the three nanowires are progressively smaller, resulting in tapered cross section silhouette you'd more likely see at Rockefeller Center than on a chip. (Unfortunately no images of the transistor will be available until 8 December.)
More than the design of the transistor, the real breakthrough for the so-called 4-D transistors was the coating of the nanowires with a new dielectric layer material made from a combination of lanthanum aluminate and aluminum oxide. This new dielectric layer allowed the researchers to use indium-gallium-arsenide, dubbed III-V semiconductor materials, in place of silicon.
Combining elements from group III of the periodic table, including indium and gallium, with those from group V, such as arsenic, has been suggested as a replacement for silicon since the 1960s. The attraction of these hybrid materials is that they can move electrons around much faster than silicon can.
One hiccup in the use of these III-V semiconductors has been reducing the dimensions of the transistor’s gate. The Purdue-Harvard team claims that their indium-gallium-arsenide transistors have 20-nanometer gates, a milestone, according to Ye.
The research will be presented at the IEEE’s International Electron Device Meeting in San Francisco, CA next week in two separate papers.
