Mix of Metal and Graphene Cools Chips

Flakes of graphene in copper or indium could let chips run faster

2 min read


Engineers at North Carolina State Univeristy report in Metallurgical and Materials Transactions B that they’ve found a better way to get the heat out of ICs. They say that flakes of the 2-dimensional wonder material graphene mixed with either indium or copper conducts heat much better than metal alone. Keeping chips cool lets you run them at a higher clock rate. In fact, how much heat chips generate was one of the motivations to moving from high-clock rate single core processors to lower clock-rate multicore ones.

The NC State researchers were working on a part of the chip package called a heat spreader. This is a layer of copper that conducts heat away from hot spots on the chip, evening out the overall temperature, and passing the heat on to a fin-shaped heat sink. The graphene-copper composite conducted heat well enough to cool 25 percent faster than pure copper (at room temperature: 380 watts per meter Kelvin for copper versus 460 watts per meter Kelvin).

You’d expect that adding a little nano to the mix would add lot of dollars to the cost. Not so here: “The copper-graphene composite is also low-cost and easy to produce,” says Jag Kasichainula, an associate professor of materials science and engineering. “Copper is expensive, so replacing some of the copper with graphene actually lowers the overall cost.”

Graphene is a hot material in the semiconductor device realm, but it’s ability to conduct heat  has been under scrutiny for a while, too. Alexander A. Balandin, chairman of materials science and engineering at the University of California, Riverside, described his research regarding pure graphene heat spreaders in the October 2009 issue, where he noted that in 2008 “my group in the electrical engineering department at UC Riverside teamed up with researchers from the physics department to carry out the first measurements of the material's thermal conductivity and found it to be above 3000 W/m K near room temperature—higher than that of diamond and on a par with that of carbon nanotubes.” Carbon nanotubes themselves have also been explored in cooling chips, but it seems that graphene is cooler than carbon nanotubes, in the social sense if not the physical one.



Photo: Dan Saelinger; Styling: Wendy Schelah; Electronics: courtesy of Tekserve

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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