MIT Makes Smallest Gallium Arsenide Transistor

At 22 nanometers, it shows compound semiconductors could take over from silicon

2 min read

Samuel K. Moore is IEEE Spectrum’s semiconductor editor.

MIT Makes Smallest Gallium Arsenide Transistor

Engineers at MIT say they’ve invented the smallest MOSFET transistor yet made from indium gallium arsenide. The transistor is just 22 nanometers long, according to a press release. The researchers hope this proves that such transistors will be ready to take over when Moore’s Law starts to sputter.

“We have shown that you can make extremely small indium gallium arsenide MOSFETs with excellent logic characteristics, which promises to take Moore’s Law beyond the reach of silicon,” says Jesús del Alamo, the electrical engineering and computer science professor who co-developed the transistor with graduate student Jianqian Lin and electrical engineering professor Dimitri Antoniadis. They described the work this week in San Francisco at the IEEE International Electron Devices Meeting (IEDM).

The International Technology Roadmap for Semiconductors recognizes indium gallium arsenide MOSFETs, in combination with germanium MOSFETs, as a potential follow-up to silicon.

IEEE Spectrumcontributing editor and compound semiconductor enthusiast, Richard Stevenson, found the advance impressive, but says it leaves open the big question of whether the MIT transistors will be manufacturable. The researchers used electron beam lithography to carve the chip’s features, a technology not used in large-scale manufacturing. Chip making today uses a form of ultraviolet photolithography and may switch to an extreme ultraviolet form within the next decade. Apart from that, the issue of what the transistors are built on will also affect their manufacturability. Stevenson comments:

MIT's work is encouraging, because it shows that you can make an indium arsenide FET at small length scales that has some good characteristics. But to make it into production at the 11-nanometer node, which will follow the 16-nm node, there's loads still to do… whatever transistor is used at the 11 nm node will have to be formed on 300 mm silicon substrates, which are the industry standard. The substrate used in this work is indium phosphide, which is smaller and far more fragile than silicon. Making indium (gallium) arsenide transistors on silicon is a very challenging task.

The MIT transistors are also of the planar variety, though the industry is rapidly moving toward 3-D devices (FinFETs), Stevenson points out. At IEDM in 2009, Purdue University researchers unveiled a gallium arsenide FinFET, but its features were much chunkier than what’s reported this week.

The bottom line is that MIT’s nanotransistor is a big step forward, but there are many, many more big steps before such devices can step in for silicon.

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