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Intel Invests $20 Billion in Ohio for Advanced Fabs

First major chip plant in the U.S. Midwest slated to begin production in 2025

3 min read
An arial view of large white building surrounded by black parking lots is embedded in a mix of farmland and forest.

A rendering of Intel's Ohio fab site as it might look when complete in 2025.

Intel

Intel has chosen to expand its advanced manufacturing in a U.S. state that neither the company nor any other chipmaker has a presence in: Ohio. Intel announced today that it will build two leading-edge logic fabs east of Columbus at a cost of US $20 billion. Construction is set to start in 2022, and production should begin in 2025, Intel says. The company gave no information about the fabs' capacities in terms of wafers per month. But it said that the site, situated on 4 square kilometers in Licking County, could be expanded over the decade for a total investment of $100 billion.

The new fabs are part of a reset of Intel's manufacturing, a plan called IDM 2.0, that would see Intel regain its ability to make chips at the most advanced nodes and offer foundry services to other companies. It also comes as the United States embarks on an effort to grow advanced chipmaking capacity. Currently, all cutting-edge chipmaking is done by Taiwan Semiconductor Manufacturing Corp. in Taiwan and Samsung in South Korea. Both companies have announced plans for new cutting-edge fabs in the United States, and the government plans to incentivize domestic production with $52 billion in incentives. The bill that would supply that money, the CHIPS Act, has passed in the U.S. Senate, but has not yet been taken up in the House of Representatives. "The scope and pace of Intel’s expansion in Ohio...will depend heavily on funding from the CHIPS Act," said Keyvan Esfarjani, Intel senior vice president of manufacturing, supply chain, and operations in a press release.

According to Intel's manufacturing road map under the IDM 2.0 plan, by the time the Ohio fabs begins production, the company's most advanced production technology will be its Intel 20A node, which it expects will bring it back into a leadership position versus TSMC and Samsung. That technology will combine a new kind of transistor—what Intel calls RibbonFET but is more generically known as the nanosheet transistor—with backside power delivery and buried power rails. The latter will allow for smaller, more efficient transistors with a degree of design flexibility that can't be achieved using today's FinFET devices. The former moves the interconnects that supply power to circuits, which are relatively large, beneath the transistors. This frees space for interconnects that carry data and signals in the area above the transistors, making chips more dense. According to Randhir Thakur, senior vice president and president of Intel Foundry Services, the Ohio site will be designed to support the next generation of manufacturing, Intel 18A, as well.

The new fabs will likely depend on the next generation of lithography systems, high-numerical-aperture extreme ultraviolet lithography. Intel issued its first purchase order for such a machine from ASML earlier this week as part of a long-term joint collaboration.

So, why Ohio? It's a fair question. “Ohio is an ideal location for Intel’s U.S. expansion because of its access to top talent, robust existing infrastructure, and long history as a manufacturing powerhouse," Esfarjani said in a press release. But the same is true of other locations.

Advanced fabs tend to cluster together for straightforward reasons: They need both specialized infrastructure—such as supplies of specialty equipment, chemicals, and gases—and a workforce trained to use it. That combination likely came into play when TSMC announced in 2020 the construction of a $12 billion fab in Arizona, where Intel already has several fabs and is spending $20 billion to build another. It's possible that with the existing expansion and competition from TSMC, Arizona was no longer attractive. But there are other tech hubs, such as the Albany, N.Y. region, that were also passed over.

In comparison, Ohio is a chipmaking frontier. Intel is likely counting on Ohio State University, located just west of its site, to supply the top end of the talent it will need. Its college of engineering has nearly 8,000 undergraduates in its program and about 1,800 graduate students. Intel says it will spend $100 million over the next 10 years partnering with local universities and community colleges. As for the infrastructure, Intel provided statements of support from chip equipment makers Applied Materials and Lam Research, fab subsystem specialist Ultra Clean Technology, and specialty gases and chemicals supplier Air Products.

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper
Green

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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