Intel Lifts the Hood on its "Single-Chip Cloud Computer"

A 48-core prototype processor is part of a move from supercomputer-on-a-chip to data-center-on-a-chip

3 min read

9 February 2010—Chips that can simulate a supernova or predict a hurricane are yesterday’s goal, if Intel’s recently unveiled 48-core research chip is any indication. Today’s goal is squeezing all the simple but extensive work of a data center onto a single chip. Big IT firms have huge, sophisticated networks of servers, says Justin Rattner, Intel’s chief technology officer and director of Intel Labs. But ”they’re not computing the mass of a proton,” he says. ”They’re searching for the needle in a haystack.”

In response to the need for better, faster data mining, Intel Labs has developed what it’s calling a single-chip cloud computer. The 1.3-billion-transistor research chip, the company reported yesterday at the IEEE International Solid-State Circuits Conference, consists of 48 Pentium-class IA-32 cores formed into a network of 24 tiles. Each tile has two cores plus one router to allow intercore communication. The keys to its efficiency at handling needle-in-a-haystack-type tasks are two new software-based techniques: one for rapidly transferring data between its many cores and the other for controlling the power those cores consume.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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