Graphene-based Tunnel Barriers Promise to Change both Electronics and Spintronics

Development marks a paradigm shift from metal oxide tunnel barriers, thereby changing forever both electronics and spintronics

2 min read
Graphene-based Tunnel Barriers Promise to Change both Electronics and Spintronics

Tunnel barriers have typically been made from metal oxides because they excel at separating conductors, such as graphene. Now researchers at the Naval Research Laboratory (NRL) have turned that all upside down by making graphene serve as a tunnel barrier for the first time

This finding by the NRL scientists is almost counterintuitive. So much work is currently done in finding ways of imbuing the conductor graphene with a band gap by using tunnel barriers. With the flow of research currently going in the direction of trying to make graphene into a semiconductor, it's unusual to have a group looking to make it serve as a tunnel barrier.

Nonetheless, in the NRL research, which was published in the ACS journal Nano Letters (“Graphene As a Tunnel Barrier: Graphene-Based Magnetic Tunnel Junctions”), the graphene serves as the electrically insulating barrier between two conducting materials. The NRL researchers were able to construct magnetic tunnel junctions, which form the backbone of read heads in the giant magnetoresistance (GMR) hard disk drives of today’s computers and magnetoresistive random access memory (MRAM), in a fully scalable lithographic process.

While GMR is a well-established technology, the area of non-volatile MRAM has been hindered by limitations resulting from the materials used. Among the big problems for MRAM has been the metal oxides used as tunnel barriers in these devices. They suffer from inconsistent thicknesses and other defects such as high resistance-area (RA) that result in high power consumption and localized heating. Graphene offers a solution to many of these problems. Because graphene is one atom thick it has very low RA, which in turn means it consumes little power but has fast switching speeds.

The NRL researchers believe that graphene-based magnetic tunnel junctions will exceed the performance of the metal oxide variety. This work represents a "paradigm shift in tunnel barrier technology for magnetic tunnel junctions (MTJs) used for advanced sensors, memory and logic," says Dr. Berend Jonker in the NRL press release covering the research.

By going against the flow of current research, the NRL researchers may have developed an alternative material that the 2011 International Technology Roadmap for Semiconductors (ITRS) believed may hold the key to creating "...electrically accessible non-volatile memory with high speed and high density [that] would initiate a revolution in computer architecture."

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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