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Graphene Makes Infinite Copies of Compound Semiconductor Wafers

Technique could reduce costs for compound semiconductor circuits and lead to new devices

4 min read
A rubber disk with a reflective copper center
Photo: Jose-Luis Olivares/MIT

Despite graphene’s amazing properties and all the engineering that has gone into giving the wonder material a band gap, its prospects for digital logic remain as much in doubt as they have ever been.

But the list of uses for graphene in electronics outside of digital logic continues to grow. The latest comes from research out of MIT in which graphene could make the use of exotic semiconductors more accessible to industries by preparing semiconductor thin films without the high cost of using bulk wafers of the materials.

In research described in the journal Nature, a thin film of graphene is placed on top of a gallium arsenide (GaAs) wafer. Then compound semiconductors—which are made of more than one element such as gallium arsenide (GaAs), indium phosphide (InP) and indium gallium arsenide (InGaAs)—are grown on top of that graphene layer in an epitaxy process.

Because the graphene is inert and thin on the substrate, the electronic potential fields emanating from the GaAs substrate can permeate through the graphene. This allows  “information” regarding the substrate’s atomic structure to pass through. In this way, GaAs film that was grown on top of graphene is able to adopt the same atomic structure as the substrate. Then after the compound semiconductors have taken shape, the graphene is slick enough to make it easy to peel off the grown semiconductor, leaving the underlying wafer unharmed.

Four images of a small flexible sheet that reads 'MIT' in blocky letters. Two of the images glow red.LEDs made using the graphene copy-machine technique.Photo: Jose-Luis Olivares/MIT

“Creating free-standing ‘single crystalline’…. thin films is a notorious challenge in the material science community,” says Jeehwan Kim, an assistant professor at MIT, in an e-mail interview with IEEE Spectrum. “The astonishing aspect of the project is that we were able to create large-scale single crystalline compound semiconductors on top of graphene, that was able to easily peel off.”

Through the use of calculations called the first-principles density functional theory (DFT) the researchers were able to model the electronic potential through a vacuum gap between the GaAs wafer and GaAs thin film. The model showed that when this gap is less than 0.9 nanometers, the GaAs substrate’s electronic potential can still interact with the arriving gallium and arsenic atoms. 

Based on these calculations, the MIT researchers knew that the atomic crystal structure of the wafer would be transferred to the compound semiconductor. The wafer serves as a crystal seed layer to grow single crystalline devices on top of it. The only desired aspect of the wafer is its polished surface, which acts as the single crystalline template, but the wafer is purposely made thicker to give it mechanical rigidity to withstand harsh processing.

A process diagram showing the crystal structure copied through a layer of graphene and then peeled awayIllustration: MIT

The need for a cheaper source of compound semiconductors is clear. There are certain properties of silicon that make it poor for certain device applications, according to Kim. For example, it’s not possible to grow high quality LEDs on top of silicon; a sapphire wafer or silicon carbide wafer is required for this device application.

“There are many more example of certain electronic/photonic devices that can hardly be brought to industry because the cost of wafers make it economically non-viable,” says Kim. “We are bringing the concept of infinite wafer re-usability specifically for this target.”

Kim says that the ultimate goal of this project achieves two things: first, to significantly bring down the cost of manufacturing exotic compound semiconductor devices; and second to create opportunities for inventing new devices.

This work also addresses the manufacturing issues that exist with marrying materials such as germanium and III-V semiconductors to silicon ICs to systems with speedier logic. Depositing these materials onto silicon tends to lead to defects that destroy device performance.

In order to grow semiconductors with minimal defects on top of silicon, the most important requirement is to ensure that the size of the crystal lattice of the film to be grown is similar to the crystal lattice of silicon, sometimes referred to as lattice matching. Unfortunately, germanium atoms are a lot larger than silicon atoms, so if you were to grown pure germanium crystals on top of silicon, the difference in the size of crystal lattice would cause lots of defects in the germanium crystals.

In this latest approach, GaAs is grown on graphene can be transferred to a silicon substrate.

“We have essentially created a stack of single-crystalline GaAs film on top of a single-crystalline silicon substrate. This how we intend to marry [compound semiconductors] with” silicon, says Kim.

One of the biggest requirements for any technology to be adopted by industry is to demonstrate large-scale processing. The current challenge for the MIT team is to scale the graphene transfer process with high yield. “There are certain areas where graphene coverage is not ideal, we want to be able to offer industries large-scale high quality graphene transfer of single-crystalline graphene,” adds Kim.

The researchers are continuing to improve the growth and exfoliation process of these compound semiconductor films, but they are more interested in creating heterostructural devices—monolithically integrated devices made of dissimilar semiconductors. To date that has been difficult to realize because of the issue of  “lattice matching” in tradition epitaxy processes.

Kim adds: “We are designing and fabricating novel devices by stacking dissimilar semiconductors on top of each. We ultimately want to amalgamate all the unique and highly advantageous properties of multiple semiconductors into one device.”

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The First Million-Transistor Chip: the Engineers’ Story

Intel’s i860 RISC chip was a graphics powerhouse

21 min read
Twenty people crowd into a cubicle, the man in the center seated holding a silicon wafer full of chips

Intel's million-transistor chip development team

In San Francisco on Feb. 27, 1989, Intel Corp., Santa Clara, Calif., startled the world of high technology by presenting the first ever 1-million-transistor microprocessor, which was also the company’s first such chip to use a reduced instruction set.

The number of transistors alone marks a huge leap upward: Intel’s previous microprocessor, the 80386, has only 275,000 of them. But this long-deferred move into the booming market in reduced-instruction-set computing (RISC) was more of a shock, in part because it broke with Intel’s tradition of compatibility with earlier processors—and not least because after three well-guarded years in development the chip came as a complete surprise. Now designated the i860, it entered development in 1986 about the same time as the 80486, the yet-to-be-introduced successor to Intel’s highly regarded 80286 and 80386. The two chips have about the same area and use the same 1-micrometer CMOS technology then under development at the company’s systems production and manufacturing plant in Hillsboro, Ore. But with the i860, then code-named the N10, the company planned a revolution.

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