Graphene Could Usher in New Silicon-based Photonic Circuitry

Reaching the "Holy Grail" of silicon photonics could be just a few years away thanks to graphene

1 min read
Graphene Could Usher in New Silicon-based Photonic Circuitry

While IBM researchers were reporting one breakthrough after another in applying graphene to electronics this year (see here and here) researchers at the University of Cambridge in the UK and CNRS in Grenoble, France were busy applying the new wonder material to optoelectronic applications.

The Europe-based researchers fabricated a device that demonstrated “the most wideband saturable light absorber ever”. But not to be outdone in applying graphene to the field of optoelectronics, IBM has quickly reported on their own research of using graphene as a photodetector in an optical link fabricated on a silicon-on-insulator (SOI) substrate.

The graphene photodetector has proven itself to be effective over a wide bandwidth between 300 nanometers to 6 microns, which could make the optical link useful for applications beyond just communications “but for remote sensing, environmental monitoring and surveillance.”

Photodectors that are effective within these wavelengths have typically been made from III-V semiconductor materials, such as gallium nitride. But in this new research by being able to fabricate the optical link on a conventional SOI substrate the possibility of fabricating photonic circuits with CMOS processes seems as though it may be within reach.

As the author of the EE Times article speculates on his own blog

“Silicon photonics is the holy grail of optical communications, enabling cheap integrated optics that handle all high-speed communications among chips and even among on-chip cores. Now IBM has demonstrated the last piece of the photonics toolkit--an optical receiver on a silicon-on-insulator substrate (SoI). Look for optical chips that integrate graphene with CMOS in five years.”

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3D-Stacked CMOS Takes Moore’s Law to New Heights

When transistors can’t get any smaller, the only direction is up

10 min read
An image of stacked squares with yellow flat bars through them.
Emily Cooper

Perhaps the most far-reaching technological achievement over the last 50 years has been the steady march toward ever smaller transistors, fitting them more tightly together, and reducing their power consumption. And yet, ever since the two of us started our careers at Intel more than 20 years ago, we’ve been hearing the alarms that the descent into the infinitesimal was about to end. Yet year after year, brilliant new innovations continue to propel the semiconductor industry further.

Along this journey, we engineers had to change the transistor’s architecture as we continued to scale down area and power consumption while boosting performance. The “planar” transistor designs that took us through the last half of the 20th century gave way to 3D fin-shaped devices by the first half of the 2010s. Now, these too have an end date in sight, with a new gate-all-around (GAA) structure rolling into production soon. But we have to look even further ahead because our ability to scale down even this new transistor architecture, which we call RibbonFET, has its limits.

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