Fantasy Sports Prep: Semiconductor Edition

David Kanter reviews and analyzes the 32nm process technologies presented at IEDM 2008 and VLSI 2009.

2 min read
Fantasy Sports Prep: Semiconductor Edition

IMAGE CREDIT: Wikimedia user Inductiveload


I'll be at Hot Chips in late August, along with the rest of the engineering press (eat your heart out, Perez!). In some ways you might say Hot Chips kicks off chip season, which continues to the International Electron Devices Meeting (IEDM) in December and culminates in the superbowl of chip-talk at the International Solid State Circuits Conference (ISSCC) in February.

In case you want to do some research for your fantasy semiconductor team, Real World Technologies' David Kanter has compiled an excellent post-game analysis of the 32nm process technologies rolled out at IEDM 2008 and ISSCC 2009. In particular, he discusses the semiconductor industry's move to 32nm manufacturing processes with high-k dielectrics and metal gates (HKMG). (I'd like to point out here that it's not all about process technology: the cyborg moth at ISSCC was so creepy I thought I had woken up in a dystopian Arnold Schwarzenegger movie. Is that reference dated now? Who's the new Arnold-- anyone care to update my pop culture database? But I digress.)

David was kind enough to summarize the article for me. However, you should still go read the whole thing yourself because this is the version for people who are easily distracted by robo-moths and Arnold Schwarzenegger's falling star.

New manufacturing technologies are essential to keeping Moore's Law on-track and driving continued advances in microprocessors, graphics processors, FPGAs, ASICs, networking and other industries that rely on semiconductor technologies. At IEDM 2008 and VLSI 2009, leading edge manufacturers announced their initial results for 32nm process technologies, discussing key techniques including transistor strain, immersion lithography, double patterning and for some, custom illumination.

The process technologies analyzed include:

1.  IBM and AMD's research work on a HKMG 45nm process using silicon-on-insulator (SOI), which is not expected to go into production.

2.  IBM and the Common Platform's HKMG 32nm bulk process

3.  Intel's high performance HKMG 32nm process, slated for production at the end of 2009

4.  TSMC's performance optimized HKMG 32nm and 28nm process expected in 2010

5.  Intel's low power 45nm process for SOCs, the first low power process to feature HKMG

6.  Toshiba and NEC's HKMG 32nm density optimized process, which currently uses custom illumination, rather than double patterning

7.  IBM and AMD's high performance HKMG 32nm SOI process, expected to debut in late 2010.

The results for each process include key density metrics such as contacted gate pitch and SRAM cell size and transistor performance metrics such as NMOS and PMOS transistor drive strength.  We include a historical comparison that puts these newer manufacturing technologies into a historical perspective, going back as far as 130nm.  New to this year's coverage of IEDM and VLSI is a graphical comparison of density and performance for various 45nm and 32nm process technologies.

Of particular interest are several facts: First, the rest of the industry, including IBM and AMD will finally catch up to Intel's manufacturing technology, using high-k dielectrics and metal gates, at 32nm. Second, approximate parity between Intel, AMD and IBM for manufacturing CPUs. And finally, approximate parity between TSMC and the Common Platform for bulk foundry processes.

I for one would like to read more about Globalfoundries, but I imagine we'll get an eyeful of that from everyone over the next six months.

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