The European Commission wants Europe to boost its share of global semiconductor production to 20 percent by 2030, from 10 percent today. To that end, it is forwarding plans for more than €43 billion in public and private investment through a European Chips Act. To accomplish that increase in chip capacity, the legislation will approve appropriations for R&D, incentivize manufacturing, and take steps to make the supply chain more secure. Jo De Boeck, chief strategy officer and executive vice president at the Belgium-based nanoelectronics R&D center Imec, explained a proposed R&D structure and its likely impact to engineers at the 2023 IEEE International Solid State Circuits Conference (ISSCC) last month in San Francisco. The R&D segment relies on the establishment of advanced pilot line facilities, to enable a path from laboratory breakthrough to fab production, and a network of competence centers, to build up capacity for semiconductor design. De Boeck spoke with IEEE Spectrum’s Samuel K. Moore at ISSCC.
IEEE Spectrum: What would you say are Europe’s strengths today in semiconductor manufacturing?Jo De Boeck: Well, manufacturing holds quite a few things. So first and foremost, I think of semiconductor manufacturing equipment and materials. Think of [Netherlands-based extreme-ultraviolet lithography maker], ASML. If you move up to the manufacturing part, you have some of our integrated device manufacturers [IDMs] in analog and analog mixed-signal and power devices, which is, of course, quite a very important area of devices and production to be in. But clearly—and that’s part of the reason for the Chips Act—there’s no European manufacturing presence at the most advanced technology nodes.
That said, how much of the focus should be on getting that cutting-edge logic versus building on the strengths that you already have?
De Boeck: Well, if it means focusing on one is losing on the other, I think that’s a bad choice to make. I think it’s important, first of all, to keep a long enough view in mind. 2030 is like tomorrow in this industry. So if we’re looking at getting 20 percent production in Europe by 2030 and you would aim that toward being leading edge, you’re in a hard place already. Before fabs are built and technology is transferred, it will be close to the end of the decade. So we need to look further out whilst continuing to build on the strengths that are there, such as the IDMs that are producing the goodies that we just discussed.
I think the important part is to find a way to keep up the capacity of the R&D and to start training people on the design of the leading-edge nodes. If there’s no demand [from chip-design firms], there will be no economical reason to build a fab [in Europe].
You talked about building “capacity to innovate.” Could you just start by explaining what’s meant by that?
De Boeck: The capacity for innovation in the case of our industry means two things—the design and the technology. And they need to go hand in hand. They need to be really close to each other. One area of the capacity will be on the design platform, and that design platform will be in the cloud, accessible from many places. The idea is that there will be design capacity in each and every member state through competence centers.
The design capacity is then balanced by the innovation in semiconductor technology. That will be carried out in larger facilities, because there needs to be focused investments there. These will be connected to competence centers for specific expertises and for design enablement on a pilot line. So the pilot line/competence center combination is the innovation capacity.
You also mentioned virtual prototyping as part of the plan. Please explain what you mean by that and what its role is.
De Boeck: I can explain by the example of back-side power delivery network technology. [Ed: This is a technology expected to debut in two or three years that delivers power to transistors from beneath the silicon instead of from above as is done now.] It’s something where the design community needs to get its hands on to do system-level exploration to see how, for instance, a back-side power distribution network could help the performance of a circuit improve. All of this requires this interplay between technology, electronic design automation vendors, and the design community. This has to be done first at a modeling and virtual prototyping phase, before you can make full silicon.
You stressed the importance of full-stack innovation. Please explain.
De Boeck: Full-stack means different things to different disciplines. But take, for example, the interplay between sensing and compute in the car of the future. That, of course, will involve a high-performance computer that needs to talk to the environment whether we’re talking to the other traffic elements—pedestrians, bicycles, cars, etc.—or understanding weather conditions That will require a lot of sensors in the car whose data must be fused by the computer. If you don’t know how this data will enter the sensor fusion engine, how much preprocessing you want to do on the sensor, you may be focusing on a suboptimal solution when developing your sensor or system architecture. Maybe you need to have a neural network on your radar to convert the raw data to early information before sending it to the central engine where it’s going to be combined with the camera input and whatever else is needed to build a full picture around the car or in its environment. A situation like that will require every element of that full stack to be co-optimized.
How can the EU Chips Act actually help make that happen?
De Boeck: Well, I think in general terms, it could stimulate collaboration. It could help to create awareness and start training people in this context because you need youngsters to start looking at the challenges in this particular way.
Samuel K. Moore is the senior editor at IEEE Spectrum in charge of semiconductors coverage. An IEEE member, he has a bachelor's degree in biomedical engineering from Brown University and a master's degree in journalism from New York University.