The July 2022 issue of IEEE Spectrum is here!

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A group of electrical engineers from Toronto, Canada, felt left out of the whole online collaboration boom. After all, folks could edit text, spreadsheets, and presentations on Google Docs and code together with GitHub. But online collaboration wasn’t really available to hardware designers.

The three, Zak Homuth, Michael Woodworth, and Steven Hamer, started the company Upverter to create what they say are the first cloud-based EE tools, working for the past year, in Homuth's parents basement and then for six months at startup incubator Y Combinator in Silicon Valley. They built tools for drawing schematics in HTML5, and launched a crowd-sourced library of parts and design tools. They tested the service with 500 Alpha users, then, at DemoFall 2011 held this week in Santa Clara, Calif., they opened Upverter to the public, reporting excitedly that 1000 new users signed on in the first day. Homuth explains Upverter in the video above. Says Homuth “If it plugs in or turns on it can be designed faster in Upverter.” More from Homuth in the video above.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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