Chips Go Vertical

Looking for new ways to make ultrafast chips, designers explore the third dimension

11 min read

Vanishingly small transistors have made Moore's Law as much a pop culture phenomenon as a driver for the semiconductor industry. By doubling the number of transistors per microchip every two years, chip makers have given us ever more powerful PCs and electronic gadgets at prices that shrink almost as fast as transistors do. So it may come as a surprise to many that today wires, not transistors, are determining the performance and cost of microchips [see figure, " Delays, Delays"].

Engineers have been figuring out more efficient ways to connect transistors since the first silicon wafer was diced into chips. When he created the integrated circuit at Texas Instruments Inc., in Dallas, over 40 years ago, Jack Kilby had to overcome the so-called tyranny of numbers that engineers of his era labored under as they tried to connect individual transistors the size of pencil erasers to perform useful calculations. The more transistors they tried to use, the more wires they needed and the more power these devices consumed. Scaling up kludged-together devices so they could do useful work would have been next to impossible--too heavy, too expensive, and too hot to handle. TI's Kilby came up with a way to integrate the elements, embedding a transistor, a capacitor, and resistors into a semiconductor material and connecting them with wire bonds to form a working integrated circuit, whereas Fairchild Semiconductor's Jean Hoerni and Robert Noyce developed approaches for planar interconnection of transistors.

The digital revolution made possible by the IC has been racing along ever since. We've managed to reduce a roomful of 1960s-era computers to a tiny wisp of silicon and as a result live in a world defined by pervasive computing and constant mediated communication. With our cellphones we snap photos of our toddler taking her first steps and let Grandma see them seconds later. We store our entire music collection in MP3 format in a shirt pocket. We talk to our cars, and the GPS map in the dashboard tells us how to get where we need to go. Every day, hundreds of millions of people swap ideas, information, cash, and products over the Internet. Our telescopes show us the edge of the universe, and our robots crawl on Mars. And there doesn't seem to be an end in sight. The latest Itanium microprocessor from Gordon Moore and Robert Noyce's old company, Intel Corp., code-named Madison and due out this year, will pack 410 million transistors into a 374-square-millimeter area. Madison's successor, Montecito, will include more than 1 billion transistors.

But guess what? The tyranny of numbers is back--albeit in a new and even more insidious guise. As ICs become more complex, so too does their wiring: some of today's chips made with wires 90 nanometers wide have a mind-boggling 7 kilometers of interconnects per square centimeter. To connect an exponentially increasing number of transistors in the same footprint, wires are built in layers.

There are local wires at the lower levels of the chip, next to the transistors that are built into the chip's silicon foundation, called a substrate. These carry signals from transistors that are relatively close to each other, within a certain circuit or functional block, say, a video decoder or chunk of dynamic random-access memory (DRAM). And there are so-called global interconnects located in the upper layers of the chip, which carry signals from transistors spaced far from each other, say, from the video decoder to the DRAM. Now, up to nine layers of wires connect transistors. Because leading-edge chips have so many interconnect layers, those wires dominate the cost of the chip, and the decision to add yet another layer has become an important one.

Beyond cost considerations, engineers are worried about performance. As semiconductor manufacturing technology progresses from one generation to the next, the time it takes for the transistor to turn on or off, or the gate delay, decreases and the chip runs faster. But global connections counteract the performance gain of these faster-switching transistors, because these wires can handle only so much speed. And in the process long interconnects consume power as unwanted capacitance, caused by all of these wires' being packed together in such a small space.

Cosmologists theorize that the fastest way to travel from one end of the universe to another is through a wormhole, which brings distant points together. Similarly, chip designers are warming to the idea that the best way to lower capacitance, maintain signal integrity, and keep chips blazing along at ever faster multigigahertz speeds is to find a shorter distance between two points. Such minimization will happen along the z, or vertical, axis. Companies have already started to stack individual chips, or dies, to make three-dimensional ICs. As they sandwich analog, digital logic, and memory circuits, they also create the IC version of a wormhole, called a via, a tiny tunnel they later thread the global interconnects through.

If it sounds a bit far-fetched, consider some of the leading alternatives: getting rid of the physical wire altogether and instead using light, radio waves, or microwaves for global interconnects. It may make a lot of sense to use these methods between chips [see "Linking With Light," IEEE Spectrum, August 2002, pp. 32­36], but using them to connect points on the same chip might add complexity and expense that offsets some of the gain. Still other blue-sky proposals involve nanotubes, spin-coupling, and molecular interconnects.

Such methods aimed at changing the fundamental nature of the wire interconnect won't rescue Moore's Law for another decade, if ever. But there are a number of other approaches to chip architectures that are being used today to increase the performance of ordinary copper wires.

Over the past year or so, semiconductor manufacturers started using a new kind of standard substance, called a low-k dielectric material, to insulate on-chip wires. This material lets them pack in more wires by reducing the capacitance between them. But at some point within the next five years, the wiring layers will fill up, and adding another wiring layer will be prohibitively expensive, unreliable, or simply impossible. So designers have come up with new ways to make the most of what they already have.

Three-dimensional chips are one of three basic strategies for getting around the interconnection conundrum. Another one is the X Architecture, promoted by the X Initiative, Mountain View, Calif. The idea is to give designers the option of using 45-degree angles to connect transistors, where the industry has relied almost exclusively on 90-degree connection routes (dubbed Manhattan layouts for their resemblance to New York City's street grid). The addition of 45-degree angles in the global interconnect layers shortens global wire lengths and opens up some room in the global layers for more wires.

Another contender is the network-on-a-chip approach licensed to chip makers by Sonics Inc., Mountain View, Calif. The basic idea is easy to grasp: put all high-bandwidth and low-latency interconnects on short wires so the longer wires in a chip will handle only the low-bandwidth, global signals that are relatively tolerant of latency. For example, the central processor of a microprocessor would have to communicate asynchronously with on-chip memory in a message-based way, much as servers communicate with client computers using data packets.

With all of these possible solutions vying for attention and development funds, one of the most audacious ideas among them is beginning to rise above the crowd. A 3-D IC is a stack of multiple dies with many direct connections tunneling through them, dramatically reducing global interconnect lengths and increasing the number of transistors that are within one clock cycle of each other. The key to the advantage comes from allowing wires to be routed directly between and through the chips. With this approach, the maximum global-interconnect length and the average global-interconnect length both decrease by a factor equal to the square root of the number of dies being stacked. This decreases the bottleneck effect they have on the IC's performance by about the same factor.

The idea should not be confused with 3-D packages, in which different functions--say, memory and logic--are put on different chips and then wired together in the same package [see "Packages Go Vertical," Spectrum, August 2001, pp. 46­51]. A 3-D package simply stacks multiple dies inside one package and connects them through wires bonded at the edges of the chips. The 3-D IC technology, on the other hand, makes possible certain kinds of chips that are otherwise cost prohibitive or difficult to produce.

Mixed-signal chips, which combine analog processing elements, such as antenna or pixel arrays, with digital elements, such as microprocessors and memories, are difficult and expensive to make in conventional planar chip-making processes. When you keep the analog functions on one chip and the digital functions on one or two other chips and combine them in a 3-D IC, yields rise and costs plummet. Thus, things like cellphones and digital cameras become a lot cheaper. New applications also become possible, such as the artificial retina being developed at Tohoku University in Japan. The device combines a quartz glass layer with an array of photodiodes that act as photoreceptor cells would in a human eye. Vertical interconnects link the photoreceptor layer to a layer of silicon circuits that convert the analog signal to bits and pass the digital signals on to the bottom layer of silicon circuits, where the image is processed and patterns recognized.

Indeed, 3-D integrated circuits give designers a path forward to cheap and reliable manufacturing of a whole array of digital-imaging, display, and optoelectronic applications. Breaking up the chip into different levels for discrete tasks means the choice of substrate no longer constrains the designer. Take, for instance, the 3-D imaging chip being developed at the High Density Electronics Center at the University of Arkansas, for the Defense Advanced Research Projects Agency. The DARPA chip has a pixel array for photo detection that sits on the top layer and digital processing circuits in the levels below. Instead of each detector signal's queuing to get off the detector chip to go to a signal-processing chip, the signal-processing circuitry is right there under each pixel, allowing the imaging system to take and process thousands of pictures per second.

The pixel array can use nonsilicon materials such as gallium nitride or indium phosphide to extend the spectral range into the infrared and ultraviolet wavelengths. This makes possible a variety of imaging applications at increased frame rates, such as ultraviolet flame sensing and combustion control, biological fluorescence detection, and pollution monitoring, as well as infrared heat sensing and chemical detection.

The most pressing reason for using 3-D interconnects is the same as the typical argument for using a 3-D package. In many instances, manufacturing all of the necessary circuitry--analog, logic, and memory--on a single chip is either impossible or much more expensive than putting it on two or more chips. Keeping different technologies on different dies and then connecting them directly using vertical interconnects lets manufacturers optimize each die's performance while keeping costs down. Furthermore, die yield decreases exponentially with increases in die size, so splitting a single die design into two or more can save money in the end. The advocates of 3-D packages are onto something: at a certain point going vertical makes sense. But since the global interconnects in a 3-D package are routed through the edges of the chips to connect to each other, their length does not decrease.

No, the way to cut global wire lengths and take advantage of faster, more reliable signals flying through your chip is to go directly vertical with your interconnects. Academics have known this for years, and ongoing projects at the Georgia Institute of Technology, the Massachusetts Institute of Technology, and Stanford University show that significant overall reductions in wire length and chip size are possible. Also, with transistors placed closer together, smaller transistors can be used to send global signals. Not only does this decrease the size of the chip by getting rid of the large, powerful transistors typically used to drive global signals long distances, but it can also decrease power consumption significantly. As chip designs get more complicated, killing two birds with one stone this way can help a great deal.

While professors have wowed people at technical conferences, the emergence of two 3-D interconnect companies signals the commercial viability of the approach: Tru-Si Technologies of Sunnyvale, Calif., and Ziptronix Inc. of Morrisville, N.C., have received funding from Intel and Xilinx, respectively. These two companies have inspired several firms to quietly launch their own R and D projects. These other firms' lab directors have seen 3-D interconnect technologies of various kinds since the early 1980s, but they have not progressed from lab to fab yet. The most recent work has been focused on bonding an arbitrary number of independently processed chips and making through-contacts between them. But as with any new technology, there are a number of ways to go from x and y to z.

The simplest case of 3-D interconnection is face-to-face interconnection of two dies, using a process called flip-chip-on-chip. Instead of its input/output coming off its edges, a flip-chip has all of its I/O come through bond pads placed at the top of the chip. Solder balls are deposited onto the pads while the chip is still part of a wafer. Then the wafer is diced into single chips, which are then placed upside down in packages--or flipped. In the flip-chip-on-chip process, the bond pads that carry the global signals out of two chips are lined up and connected using solder connections. Since there are two strata in this case, global-interconnect lengths can be reduced by about 30 percent.

Flip-chip-on-chip has been around for years. The more complex approach touted by Tru-Si and Ziptronix involves direct vertical interconnection, with wires that run straight through the substrates of each chip. This requires that vias, or through-holes, be made in the chips to allow those wires to go through. The advantage to these methods is that you'll eventually be able to stack more than two chips together.

You can make these vias either before (via-first) or after (via-last) you bond the chips together. The via-first approach is the most widely used and is championed by researchers at the Association of Super-Advanced Electronic Technologies laboratory, University of Arkansas, Rensselaer Polytechnic Institute, State University of New York at Albany, Fraunhofer Institute, and Tru-Si. Using this method, blind vias, which do not go all the way through the wafer, are formed in the wafer either while the transistors are being made or immediately after. These vias are coated with a layer of insulating material before the conducting metal, typically copper, is deposited to make the wire. The wafer is thinned from the back until the wires are exposed, at which point the next wafer can be attached to the back of the thinned wafer, front-to-back.

Meanwhile, the via-last approach pioneered by Ziptronix is gaining acceptance [see figures, " Pick and Place" and " All Wired Up"]. For Ziptronix's 3-D IC application, the global interconnects are formed at the top of chips on a wafer, which can be thinned to less than 10 micrometers and polished precisely to create an atomically smooth surface. Individual chips are then stacked face down on top of the chips in the wafer using a covalent bonding technology. The two bonding surfaces are chemically treated so that when they are put in contact at room temperature, they form the same kind of seamless, permanent covalent bonds that hold the atoms together in the bulk material.

Then the vias are etched into the back of the face-down chip, reaching through to bond pads on the front. The through-wires are made using the same kind of insulating and deposition process used for the via-first approach. In a three-chip stack, the next wafer can then be bonded face-to-back and the process repeated, though so far the company has demonstrated only two-chip stacks. The company has produced highly reliable test samples with 2-µm-diameter vias spaced 7 µm apart, meaning that more than 20 000 interconnects can be jammed into each square millimeter while using 6 to 8 percent of the silicon surface area.

With either the via-first or the via-last approach, there is the question of whether to bond one chip at a time or to bond whole wafers together and thus bond many chips at once. Such wafer-level stacking can be done so that there is always at least one full-thickness wafer in the stack, which simplifies handling. From a yield perspective it is questionable, because the yield of the stacked devices becomes the product of the yields of the wafers. A bad die would cancel out the good one to which it is bonded. One way to boost yields is to fully test each wafer to find out where the bad dies are. Once you know this, you can bond wafers that have their bad dies in the same places, so bad dies line up with bad dies, good with good.

Optimizing yield for 3-D ICs can be tricky, and cost is always a factor in any manufacturing decision. In general, the via-first approaches hold the best promise for low cost, because the vias can be made and filled with little additional cost while the transistors are made. The via-last approaches have the best chance for high yield, because the vias are not made blindly. That is, in the via-last process holes can be made precisely where they are needed, whereas in the via-first process the holes are placed where you think they will be needed.

The one big drawback to all 3-D ICs is that silicon surface area, enough for thousands of transistors, is sacrificed. However, global-interconnect limitations will force designs to have wasted space anyway. By the time you get to wires with 45-nm widths, the chip will need to have more area than the transistors need, just so the wiring will fit. This means there will be unused silicon real estate in each cutting-edge chip. If you can't put that real estate to use by putting transistors on it, you can by routing a wire through it.

Since the global interconnects on the top wiring layers will determine the chip area, not the little wires down by the transistors, there will be some freedom to put the transistors where you want them without changing the chip area. You can bunch the transistors together to make large open areas, instead of having many small plots of empty space throughout the chip. Then you can use those large areas for through-hole wires without losing any more real estate than you are already losing.

Ultimately, cost and yield will decide whether 3-D ICs make it into the fab and onto the market. So far, Infineon Technologies AG, in Munich, and IBM Corp. are the only chip makers that have announced their 3-D IC technology work, though others are certainly working on it. In the months to come, expect to see announcements about partnerships with Tru-Si and Ziptronix from companies that can't afford to brew their own 3-D IC processes.

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