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Carbon Nanotubes Could Solve Problems With Silicon in Li-ion Batteries

By coating carbon nanotubes with silicon, the problem of silicon breaking up after charge/discharge cycles could be solved

2 min read
Carbon Nanotubes Could Solve Problems With Silicon in Li-ion Batteries

Replacing graphite in the anodes of lithium-ion (Li-ion) batteries with silicon, or variations of nanostructured silicon, in order to boost the time between charges has been the main focus of research for years now.  I have been covering these developments for the last six years because of my interest in having a smart phone that can manage to get through half a day without needing a recharge. 

The big buzz of late has been the use of graphene in the anodes of Li-ion batteries, with the aim of powering all-electric vehicles.

Researchers at North Carolina State University have not only returned to our former favorite nanomaterial, carbon nanotubes, for solving the problems of replacing graphite with silicon, but have also taken the sensible approach of making mobile devices the target application for the improved batteries.  Okay, they do mention electric vehicles in the press release announcing the results, but I can at least hope that they are swayed by the indications that Li-ion batteries, no matter how good we make them, will not be entirely effective in all-electric vehicle applications. And there has been no stronger indicator of this than the consumer marketplace, which has not been too friendly to attempts to make Li-ion batteries work for all-electric vehicles.

The researchers, who published their findings in the journal Advanced Materials (“Aligned Carbon Nanotube-Silicon Sheets: A Novel Nano-architecture for Flexible Lithium Ion Battery Electrodes”), used silicon as a coating on the carbon nanotubes (CNTs). The CNTs are aligned in one direction; this structure ensures controlled expansion of the silicon so that when it expands and contracts it’s less likely to start breaking apart.

“There’s a huge demand for batteries for cell phones and electric vehicles, which need higher energy capacity for longer driving distances between charges,” said Xiangwu Zhang, associate professor of textile engineering, chemistry and science at N.C. State, in a press release. “We believe this carbon nanotube scaffolding potentially has the ability to change the industry, although technical aspects will have to be worked out. The manufacturing process we’re using is scalable and could work well in commercial production.”

I know I am supposed to be impressed by waterproof mobile phones, but I would give up that feature in a second for a smart phone that lasted an entire day without recharging—maybe even two days.

Photo: Wiley-VCH Verlag/KGaA

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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