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Nanotubes and Graphene Foam Make Hybrid Energy Storage Device

Researchers create hybrid between supercapacitors and pseudocapacitors with energy density close to that of batteries

2 min read
Nanotubes and Graphene Foam Make Hybrid Energy Storage Device
Photo: University of California, Riverside

A paper in the journal Science earlier this year suggested that the problem of nomenclature for energy storage devices—specifically, defining the difference between what is a supercapacitor and what is a pseudocapacitor—is beginning tohold back development in the field.

To confuse matters further, researchers out of University of California Riverside have now developed an energy storage device that they define as a hybrid between a supercapacitor and a pseudocapacitor, but they prefer to term simply a supercapacitor.

The research, which is published in the journal Nature Scientific Reports, used hydrous ruthenium oxide (RuO2) nanoparticles that were modified by carbon nanotubes (CNT) and graphene foam as the electrode material for the supercapacitor. They then put the electrodes in an aqueous electrolyte. The combination not only operated safely, but also provided more energy and power density than what today’s commercially available supercapacitors can give.

“Besides high energy and power density, the designed graphene foam electrode system also demonstrates a facile and scalable binder-free technique for preparing high energy supercapacitor electrodes,” said graduate student Wei Wang in a press release. “These promising properties mean that this design could be ideal for future energy storage applications.”

The graphene-and-nanotube hybrid foam was  dipped into a slurry of the RuO2 resulting in a few-layer-thick graphene foam architecture covered with hybrid networks of RuO2 nanoparticles and anchored nanotubes. This design merges the supercapacitor’s high  conductivity and pseudocapacitor’s high specific capacitance, according to the researchers.

“The resulting hybrid device enables enough electrolyte access to the active materials (CNT-RuO2 network layer),” Wang told the Nanoclast in an e-mail. “And at the same time, the embedded CNTs in the CNT-RuO2 network layer work as a conductive framework.”

Supercapacitors operate in the space between batteries and traditional capacitors when it comes to the metrics of energy density (the amount of energy stored per unit mass) and power density (the maximum amount of power that can be supplied per unit mass). Batteries can store a lot more energy than supercapacitors and capacitors can deliver power far more quickly than supercapacitors. However, since supercapacitors can deliver power fast and charge up quickly in comparison to batteries, they are attractive for many applications, like electric vehicles, where they could be charged up in minutes rather than hours. But compared to batteries supercapacitors have low energy density, so the aim has been to increase how much energythey can store. If supercapacitor energy density could be increased, they could potentially replace chemical-based batteries.

While nanomaterials have been touted as good alternatives to traditional activated carbon for supercapacitor electrodes, it’s not been clear that they can provide enough surface area to make the resulting devices match the energy density of lithium-ion (Li-ion) batteries. On average those batteries have a specific energy density of 200 Watt-hour/kilogram,  whereas today’s supercapacitors can get around 28 Wh/kg. In figures released by the UC Riverside researchers, they claimed a full cell energy density of their device of 39.28 Wh/kg. Whether this will be enough to really be a breakthrough for supercapacitors in all-electric vehicles remains to be seen.

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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