Building 3D Batteries from the Bottom Up with Coated Nanowires

Building 3D batteries with nanowires allows scaling of thickness without compromising lithium-ion kinetics seen with thin-film batteries

2 min read
Building 3D Batteries from the Bottom Up with Coated Nanowires

To continue on with the string of nanotechnology developments at the end of last year (here and here) that were aimed at improving the battery, I start this New Year with another such story this time coming from researchers at Rice University.

This news actually broke in December when it was originally published in the December 6th online edition of Nanoletters.

The research, which was led by Pulickel Ajayan, managed to find a way to coat nanowires with PMMA coating that provides good insulation from the counter electrode while still allowing ions to pass easily through.

This minimized separation between two electrodes manages to make the battery much more efficient.

"In a battery, you have two electrodes separated by a thick barrier," said Ajayan, professor in mechanical engineering and materials science and of chemistry. "The challenge is to bring everything into close proximity so this electrochemistry becomes much more efficient."

To achieve this, the Ajayan and his lead researchers Sanketh Gowda and Arava Leela Mohana Reddy took the concept of 3D batteries and coated millions of nanowires to create the 3D structure from the bottom up.

“We wanted to figure out how the proposed 3-D designs of batteries can be built from the nanoscale up," said Gowda, a graduate student in Ajayan's lab. "By increasing the height of the nanowires, we can increase the amount of energy stored while keeping the lithium ion diffusion distance constant."

As Gowda readily admits in the news release, 3D designs are nothing new. However, the achievement here was the process they developed for coating the nanowires in the PMMA without any break in the coating.

The process involves the growing of 10-micron-long nanowires through electrodisposition in the pores of an anoidized alumina template. They then drop-coated PMMA onto the nanowire array resulting in an even casing from top to bottom. 

The result of this work is ultimately expected to be batteries for scalable microdevices that possess a greater surface area than thin-film batteries.

 

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3 Ways 3D Chip Tech Is Upending Computing

AMD, Graphcore, and Intel show why the industry’s leading edge is going vertical

8 min read
Vertical
A stack of 3 images.  One of a chip, another is a group of chips and a single grey chip.
Intel; Graphcore; AMD
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A crop of high-performance processors is showing that the new direction for continuing Moore’s Law is all about up. Each generation of processor needs to perform better than the last, and, at its most basic, that means integrating more logic onto the silicon. But there are two problems: One is that our ability to shrink transistors and the logic and memory blocks they make up is slowing down. The other is that chips have reached their size limits. Photolithography tools can pattern only an area of about 850 square millimeters, which is about the size of a top-of-the-line Nvidia GPU.

For a few years now, developers of systems-on-chips have begun to break up their ever-larger designs into smaller chiplets and link them together inside the same package to effectively increase the silicon area, among other advantages. In CPUs, these links have mostly been so-called 2.5D, where the chiplets are set beside each other and connected using short, dense interconnects. Momentum for this type of integration will likely only grow now that most of the major manufacturers have agreed on a 2.5D chiplet-to-chiplet communications standard.

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