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Building 3D Batteries from the Bottom Up with Coated Nanowires

Building 3D batteries with nanowires allows scaling of thickness without compromising lithium-ion kinetics seen with thin-film batteries

2 min read
Building 3D Batteries from the Bottom Up with Coated Nanowires

To continue on with the string of nanotechnology developments at the end of last year (here and here) that were aimed at improving the battery, I start this New Year with another such story this time coming from researchers at Rice University.

This news actually broke in December when it was originally published in the December 6th online edition of Nanoletters.

The research, which was led by Pulickel Ajayan, managed to find a way to coat nanowires with PMMA coating that provides good insulation from the counter electrode while still allowing ions to pass easily through.

This minimized separation between two electrodes manages to make the battery much more efficient.

"In a battery, you have two electrodes separated by a thick barrier," said Ajayan, professor in mechanical engineering and materials science and of chemistry. "The challenge is to bring everything into close proximity so this electrochemistry becomes much more efficient."

To achieve this, the Ajayan and his lead researchers Sanketh Gowda and Arava Leela Mohana Reddy took the concept of 3D batteries and coated millions of nanowires to create the 3D structure from the bottom up.

“We wanted to figure out how the proposed 3-D designs of batteries can be built from the nanoscale up," said Gowda, a graduate student in Ajayan's lab. "By increasing the height of the nanowires, we can increase the amount of energy stored while keeping the lithium ion diffusion distance constant."

As Gowda readily admits in the news release, 3D designs are nothing new. However, the achievement here was the process they developed for coating the nanowires in the PMMA without any break in the coating.

The process involves the growing of 10-micron-long nanowires through electrodisposition in the pores of an anoidized alumina template. They then drop-coated PMMA onto the nanowire array resulting in an even casing from top to bottom. 

The result of this work is ultimately expected to be batteries for scalable microdevices that possess a greater surface area than thin-film batteries.


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The First Million-Transistor Chip: the Engineers’ Story

Intel’s i860 RISC chip was a graphics powerhouse

21 min read
Twenty people crowd into a cubicle, the man in the center seated holding a silicon wafer full of chips

Intel's million-transistor chip development team

In San Francisco on Feb. 27, 1989, Intel Corp., Santa Clara, Calif., startled the world of high technology by presenting the first ever 1-million-transistor microprocessor, which was also the company’s first such chip to use a reduced instruction set.

The number of transistors alone marks a huge leap upward: Intel’s previous microprocessor, the 80386, has only 275,000 of them. But this long-deferred move into the booming market in reduced-instruction-set computing (RISC) was more of a shock, in part because it broke with Intel’s tradition of compatibility with earlier processors—and not least because after three well-guarded years in development the chip came as a complete surprise. Now designated the i860, it entered development in 1986 about the same time as the 80486, the yet-to-be-introduced successor to Intel’s highly regarded 80286 and 80386. The two chips have about the same area and use the same 1-micrometer CMOS technology then under development at the company’s systems production and manufacturing plant in Hillsboro, Ore. But with the i860, then code-named the N10, the company planned a revolution.

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