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A Flash Memory That Doubles as DRAM

Engineers work to combine volatile and nonvolatile memory into one flash device

4 min read

3 March 2011—Engineers at North Carolina State University (NCSU) have refurbished flash memory in an attempt to create something new: a "unified memory" type that can be fast but volatile, like the memory workhorse dynamic RAM, or slow but nonvolatile, like the flash storage in MP3 players. At this point, the team has simulated only one memory cell’s behavior and made a proof-of-concept prototype, but they believe that their design may lead to instant-on computers and power savings in today’s behemoth data centers.

Of course, IEEE Spectrum readers have heard such memory claims before. More exotic memory technologies— resistive, phase change, even spintronic devices—are also contenders for the guts of imagined instant-on machines. The new flash’s advantage, says one of the NCSU designers, Daniel Schinke, is that it’s less adventurous: "Our device is also new, but the technology behind it is very mature."

Traditional flash works by forcing charge onto a layer of metal or polycrystalline silicon called a floating gate. In terms of bits, charge on the gate represents a 1, and an absence of charge stands for a 0. A barricade of dielectrics surrounding the gate keeps the charge from escaping, even when the memory has no power. Alternatively, DRAM is much faster, keeping electrons in capacitors that charge quickly but need energy to keep their state.

The NCSU flash has two floating gates instead of one. Storing all of its charge on the bottom gate, the flash can act like its old nonvolatile self. But by using the second gate and a continuous source of power, it can work more quickly, shuffling preset proportions of charge between each of the gates to represent a 1 or a 0.

Tuo-Hung Hou, a professor of electronics engineering at National Chiao Tung University, in Taiwan, who did not work on the NCSU device but who also researches modified flash memories, agrees with Schinke. "The proposed [device] is attractive," he says, "because it is based on very scalable, cheap, and production-proven technology." But to realize the promised applications, he says, the team will first need to prove that the design can perform as predicted in simulations, and he believes that getting it to operate in both modes without interference "might be challenging."

Part of that challenge will be repurposing memory that is now optimized mainly to keep its content, not to endure many rewrite cycles, as DRAM is. The problem with traditional flash is that it requires a strong electric field set up in the dielectric to pull the charges from an electron channel onto the floating gate. Over many write cycles, that field can wear the dielectric down, making it easier for the electrons to escape. After some 100 000 rewrites, flash’s capabilities decline, but DRAM can survive though 10 orders of magnitude more cycles.

The NCSU researchers, led by professor of electrical and computer engineering Paul Franzon and colleague Neil Di Spigna, think that using two closely neighbored floating gates could take the burden off the dielectric and make for faster memory in volatile mode. Between the channel and the gates, the device would have a thick layer of dielectric, as traditional flash does. But the dielectric layer between the two gates would be much thinner—thin enough to allow electrons to use direct tunneling from one gate to the next, a special form of quantum tunneling that can better preserve the dielectric. For dynamic programming, charge has to move only between the two floating gates. "We’re using a gentle mechanism," Franzon says, as opposed to the strong electric fields used for more "harsh" charging in traditional flash. That type of charging uses either a messier version of tunneling or forces the electrons to travel inside the dielectric.

Tunneling the electrons more gently between gates might allow the large number of rewrite cycles found in more expensive DRAM, Franzon says. In nonvolatile mode, the device would pull charge from the electron channel using traditional means, cramming as much of it as possible into the lower, better-barricaded gate. In volatile mode it would use a constant supply of energy to quickly divvy the charge between the two gates and hold it there using electric fields.

Before the power is turned off, Franzon says, the state in volatile mode could be stored in the lower gate—releasing all the charge for a 0 or giving it all back to the first gate for a 1. "In milliseconds you could transfer an entire memory…and freeze its contents," Franzon says. At start-up, that would mean less travel time for the processor to begin again, and thus a near instant boot.

The ability to freeze data would also provide energy savings. Instead of powering volatile DRAM while it simply maintains the same memory, the double-gate device could temporarily store the information and cut the power until the data is really needed.

Although Albert Fazio, an Intel Fellow and the company’s director of memory technology development, encourages the team to aim for such research goals, he cautions that the dual-gate device has a way to go before implementation. "There are constraints in this approach," he says, "that still leave it fairly deep in the research field." One difficulty he foresees is proving that the device can work in the dual modes in a real memory array configuration, not just as an individual memory cell.

"It’s really the array configuration that tells you about the performance and also the cost," he says, and perhaps, he adds, whether it’s even worth unifying memory types. "If it’s more expensive than DRAM," Fazio asks, "well, then is it any better than using a discrete DRAM and a discrete flash?"

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