As the world unwires, the market for wireless communications chips has begun to soar. Market research company IC Insights Inc. (Scottsdale, Ariz.) projects a worldwide market of US $28.8 billion in 2004.
Now, a breakthrough by IBM re-searchers promises to unleash a new generation of low-power wireless-communications ICs by solving a problem that has plagued semiconductor specialists for years.
The problem revolves around the so-called mixed signal chips that are becoming ubiquitous in cellphones and wireless-equipped laptops and PDAs. These chips contain both ordinary field-effect transistors, of the sort found by the millions in ordinary CMOS ICs, and also bipolar transistors. The field-effect devices implement the logic, for example communications protocols and signal processing. The bipolar transistors, meanwhile, amplify the radio signals going into and out of the antenna. Mixing the two types of device on one chip makes for a compact and power-efficient product.
But, until recently, it also created a painful choice for designers. They could build their circuits either on wafers that minimize the power consumption and maximize the speed of the digital CMOS components or on wafers that give the fastest possible bipolar transistors.
In advanced CMOS manufacturing, devices are built in a very thin top layer of silicon, separated from the bottom silicon substrate by a layer of insulating silicon dioxide. CMOS devices built on these silicon-on-insulator (SOI) wafers use less power than identical ones built on conventional wafers.
On the other hand, the fastest bipolar transistors contain germanium in their bases, which lets them run in excess of 350 GHz, which is much faster than ordinary silicon bipolar devices can go. Built perpendicular to the substrate, they consist of the emitter on top, the base in the middle, and the collector at the bottom. Below the collector is a heavily doped region called the subcollector that provides a low-resistance path to the collector contact on the chip surface. This vertical structure allows the base to be very thin and to be doped with germanium to get the highest speeds.
Ideally, designers would like to put these devices on the same SOI wafers as the digital CMOS devices. But to do that, the bipolar transistor must fit into the thin layer of silicon at the top of the chip. The basic problem, says Ghavam Shahidi, director of silicon technology at IBM Research (Yorktown Heights, N.Y.), is that the basic bipolar device is about 2 µm thick, with most of that thickness due to the subcollector. That’s far too thick to build into an SOI wafer, where the top silicon layer is only about 0.1 µm thick.
Shahidi told IEEE Spectrum that past attempts to build bipolar transistors on SOI wafers have turned the devices on their sides so that the emitter, base, and collector are built into the substrate. In these lateral transistors, the bases are thicker than those in the vertical devices and, most important, cannot be doped with germanium. As a result, they are slower and consume more power.
So to build the best possible bipolar device on SOI, the IBM researchers made a compromise. They made the emitter-base part of the transistor vertical, allowing the base to be doped with germanium. But they bent the device just below the base and eliminated the thick subcollector. But by adding a heavily doped region below the collector contact and placing the collector contact as close as possible to the rest of the device, they were able to achieve a low collector resistance [see figure]. The collector was now thin enough to build into an SOI wafer and combine with the highest-performance CMOS circuits.
”The critical part is to have a vertical base-emitter structure for device speed, and to eliminate the thick subcollector layer so that the collector can fit into the thin silicon layer of an SOI wafer,” says Shahidi, an IBM Fellow.
The result is a bipolar transistor that consumes only one-fifth the power of previous attempts to put lateral bipolar transistors onto SOI substrates. In a paper presented last September at a conference of semiconductor researchers in Toulouse, France, IBM research staff member Jin Cai told attendees that when the feature sizes on the new device shrink to 100 nm from their present 160 nm and the thickness of the top silicon layer is reduced from 120 nm to 55 nm, he expects the transistors to run at 200 GHz. That’s not as fast as the fastest devices, but it’s close enough for most wireless communications applications.
The next step, says Shahidi, is to show the potential benefits of the device by building more complicated circuits. ”We will continue to optimize the device even more so that we come closer and closer to the best we can do in bulk,” he told Spectrum.
—Linda Geppert