Improvements to EDA and EMC Workflows in CST STUDIO SUITE 2013
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This webinar presents improvements to EDA and EMC/EMI simulation workflows in CST STUDIO SUITE® 2013, at both the component and system levels. A wireless router is used as a test case to demonstrate board and system-level SI/PI and EMC analysis.
The first half of the webinar focuses on the SI/PI analysis of the board and sets the foundation for a system-level EMC analysis. A fast SI rule-checking solver is introduced to identify potential problems based on well established rules. The goal is to analyze complex PCB layouts quickly and detect the occurrence of SI, PI and EMC design rule violations. These violations are highlighted and analyzed using highly accurate 3D full-wave simulations to allow a rigorous analysis of the potential noise sources.
The second half of the webinar focuses on EMI susceptibility issues for the system, demonstrating an efficient modeling methodology using the field source approach for noise sources such as heat sinks. The equivalent field source will be used as the basis of EMI analysis at the system level, taking into consideration the couplings to nearby components such as cables, connectors and boards. Aspects of chassis-level simulations will also be discussed, including the modeling of complex details such as vents, slots and seams using equivalent compact models that greatly reduce the complexity of the analysis.
PRESENTER:
Antonio Ciccomancini Scogna received the PhD degree in Electrical Engineering from University of L’Aquila, Italy. He is currently EDA Market Development Manager at CST of America, Framingham, MA. His research interests include EM numerical modeling, printed and integrated circuits, packaging, SI and PI analysis in high-speed digital systems. He has authored more than 70 publications and serves as reviewer for many international journals.
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