The high performance application processors found in today's mobile electronic devices such as smart phones and tablet computers require miniaturized IC packages that can satisfy the demands for compact, low-profile and lightweight products while meeting signal and power integrity performance specifications and dense routing requirements. Coreless substrate with embedded trace substrate technology has been demonstrated to be a viable solution to helping achieve package miniaturization. Compare to conventional thick core substrates, coreless substrate technology eliminates the substrate core and utilizes build-up layers to connect the chip and the motherboard. In addition to the z-height reduction, this also leads to shorter interconnections and generally has been demonstrated to improve power integrity and signal integrity performance. However the lack of a rigid and low CTE core layer has been found to result in thermal warpage issues throughout the substrate manufacturing and assembly process which induces thermal mechanical stress and strain at the interconnections. During this webinar we analyze two test vehicles, one a standard thick core symmetric design and the other a coreless substrate and compare the impact on electrical performance in terms of signal and power integrity metrics in the time and frequency domains. We also demonstrate how design optimization through asymmetry in the substrate thickness direction along with mechanical/thermal treatment and low CTE material usage are capable of improving thermal warpage issues when compared to conventional thick core designs.
Darryl Kostka is a Senior Application Engineer at CST of America where he manages the technical activities in several industry areas including the consumer electronics market. Darryl holds a Master’s in Electrical Engineering from McGill University, Montreal. His focus is on the development of simulation methodologies for Signal and Power Integrity and Electromagnetic Compatibility analysis of high-speed digital systems.
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