The first 3-D transistors to make their debut were uniform in height, and arrayed in a regular, waffle-like pattern on chips. But in the future, a birds-eye view of circuits made from these transistors may look more like a city skyline.
A Taiwan-based group led by Fu-Liang Yang at the National Nano Device Laboratories has built SRAM memory cells containing 3-D transistors that are a mix of two different heights. Building SRAM cells with this mix reduced the footprint of cells by 20 percent, they report. That can mean significant space savings at the chip level, says collaborator Chenming Hu at the University of California, Berkeley: “SRAM can occupy 50 percent or more of footprint of an advanced processor.”
Although lithography places some feature sizes off limits, for the most part the width of a planar transistor channel can be varied at will to carry as much current as is needed. Nowadays, the transistor channels used in logic circuits may be just a few dozen nanometers wide, while the transistor channels on the edges of chips can be as wide as 10 microns, Hu says, in order to accommodate the large amount of current needed for inter-chip communications.
But FinFETs, which were proposed in the late 1990’s by Hu and colleagues to stanch leaks, don’t have that flexibility. In these devices, the channel is turned on its side so that it pops out in the third dimension. A gate to control the device is the wrapped over the three sides of the resulting fin.
Early implementations of the device, such as those debuted by Intel in 2011, have had only one fin height. If a chip designer wishes to double the current going though a certain part of a circuit, he or she must double up the number of fins. Current can only be increased in single-fin increments.
But in 2011, Hu and postdoctoral fellow Angada Sachid pointed out that this sort of design “quantization” isn’t necessary. Because the FinFET is essentially just a planar transistor turned on its side, altering the height of the fin would be akin to adjusting the channel width.
The two presented simulation results at the International Semiconductor Device Research Symposium in College Park, Maryland in December 2011 suggesting the approach could have some advantages for SRAM operation in addition to cutting down on space. “We wanted to point out that you can have both. There’s no reason an entire city has to be made of tall buildings. There can be a mix of tall buildings and single family homes,” says Hu.
Yang and colleagues put this idea to the test by creating two kinds of 10-nm-long FinFETs in silicon. A shorter, 20-nm-tall version of the device was used to make the pass-gate transistors in SRAM cells, and a higher, 40-nm version was used to form the pull-down transistors, which require more current.
When the two were paired together, the team was able to create SRAM cells that were more compact than comparable cells made from FinFETs of uniform height. The new cells also proved more stable than cells of the same size that were made with single-height fins. That’s because the ratio of currents driven through the pass-gate and pull-down transistors in the SRAM cell could be more finely-tuned. The results were presented last week at the 2013 Symposium on VLSI Technology, held in Kyoto, Japan.
(Photo: Randy Faris/Corbis)