The 32-nm middle child

Intel's done it. According to Intel's roadmap, the first 32-nm chips will roll out in devices in late 2009. By now, 32-nm test chips put the node squarely in the development part of Intel's three-year research-development-manufacturing cycle.

TSMC did it in late September/early October, announcing two different 28 nanometer chip making processes slated for fabrication in 2010. IMEC did it and told us how at IEDM (immersion lithography).

The notable odd man out is AMD, which just released Shanghai in November, debuting its hot new 45-nm chip technology just in time to mark the one-year anniversary of Intel's first 45-nm Penryn chips.

With 45 nm already old hat for Intel, and 32-nm chips all set to go in Q4 of next year, all the talk at IEDM was of 22-nm and beyond. As I mentioned in my last post, this renders the 32-nm node effectively chopped liver. So what explains the middle child phenomenon?

22 is the new 45

The big advance that enabled Intel's 45 nanometer technology was the ability to contain leakage current with a new high-k metal gate (HKMG) process.

Intel in particular tends to pull out all the stops to get to one node, and then coasts through the next node. It seems intuitively obvious: you put all your R & D money into reinventing the transistor, and then you push that technology to its limits. By the time the technology has hit a brick wall, you're already working on the next big breakthrough.

For its 32-nm process, according to papers at IEDM 08, Intel is using a 2nd-generation high-k gate material. They're manufacturing the new transistors with 193-nm immersion lithography tools. That's not so radically different from what they did at 45-nm (except at 45, they used a combination of 193-nm dry tools from ASML and Nikon-- now that they've dropped ASML, their immersion litho tools are solely Nikon.) Aside from the exclusive choice of Nikon as vendor, and the new immersion litho tools, this year's IEDM papers revealed that nothing in the process had changed significantly between 45 and 32.

But for the 22nm node, it looks like Lanthanum might be the new it-metal. One of the Intel papers discussed an advanced gate stack for 22nm low operating power applications, with thin cap layers using lanthanum oxide or aluminum oxide on hafnium-based high-k.

45 is the new 90

The middle child phenomenon seems to be cyclical: consider the path from 90 nm to 65 nm node technology.*

In 2006, Geek.com reported that Intel's 65 nm process used "second generation strained silicon with a 10-15% improvement on drive current." [italics mine] When Intel announced its upcoming 90 nm technology node in 2002, strained silicon was the big breakthrough.

Strained silicon allowed Intel to coast through 65, but it stopped working at 45, which is why the CMOS transistor had to be redesigned. So, every time you have a second generation process, that means you haven't had to reinvent anything to make the node-shrink possible, meaning there's a lot less research and a lot more development at that node. Meaning you can save the R part of the R & D money for the next node.

My prediction? The next middle child will be the 16 nm node, which will exhaust the limits of the novel technologies that enable 22nm.

Further support for my crystal ball is brought to you by the New York Times Bits blog, where John Markoff hinted last week that at 11 nm, tiny transitors will be made of III-V hybrids that Intel is just starting to explore.

It might be four chip generations, however, before Intel adds the new hybrid approach to its commercial chips, said Mike Mayberry, the companyâ''s director of components research.

Intel is now solidly at 45; four more generations--32, 22, 16, 11--brings us to 11. If these fancy III-V hybrids emerge at the 11 nm node, 16 nm is sure to be the next chopped liver.


*This pattern is different for different companies. For IBM, the middle child appears to be 45 nm, which AMD is using for Shanghai, but which had been heavily delayed.

AMD has a cross-licensing agreement with IBM, which was supposed to roll out HKMG technology for the 45-nm node in 2008: but though AMD "desperately needed" high-k at 45 nm to keep up with Intel, EETimes' 2007 IEDM coverage stated that

IBM has yet to roll out high-k in a product. ... [I]n a move that raises questions about the readiness of IBM's technology, AMD said it has yet to make a commitment to use high-k at 45 nm, saying instead that the dielectric shift is an "option" at that node.

Some companies are just going to high-k at 32: now IBM and its partners have announced that their 32-nm HKMG devices will be available to IBM alliance members in the second half of 2009. That includes AMD-- but we haven't seen high k mg out of AMD in a product.

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