Actual footage of Intel's D1D production/development fab
This Conan skit explains not just what chipmakers are trying to do about the interchip communication problem, but also the problem that plagues the solution.
First: what is 3-d chip stacking and why would you do it? Stacking layers of integrated circuits atop each other is a solution to interchip communication problems detailed in a recent Spectrum article on multicore's very bad, no good, terrible day.
At the heart of the trouble is the so-called memory wall''the growing disparity between how fast a CPU can operate on data and how fast it can get the data it needs. Although the number of cores per processor is increasing, the number of connections from the chip to the rest of the computer is not. So keeping all the cores fed with data is a problem.
DARPA's exascale computing project showed that the barrier to exascale isn't flops-- we have that figured out. Now the problem is the time that data spends in the chip's wiring. The interconnect bottleneck is upon us. And if these technology trends continue, exascale computing will still be "just a dream in 2015."
To deal with the bottleneck situation, the U.S. Department of Energy formed the Institute for Advanced Architectures and Algorithms, where researchers are exploring "tighter, and maybe smarter, integration of memory and processors." Sandia, for example, is looking into stacking memory chips atop processors to improve memory bandwidth.
Solution: Go Up, Not out
It's not the world's newest idea. IBM showed 3d stacking techniques at IEDM 2002. Six years later, IEDM 2008 attacked the problem with at least 17 papers and one dedicated panel. The papers featured all the heavy hitters: Tokohu Universty, CEA-Lti Minatec, IBM's T. J. Watson Center, IMEC, NEC, and Qualcomm, among others.
Qualcomm showed that the problem is not limited to processors: memory alone will need this stacking too, especially if it's going to follow the same trend as processors-- which it surely will, given the trend toward small handheld devices with the same amount of memory as desktop computers, but with a much smaller footprint.
Belgian consortium IMEC demonstrated the viability of stacking two CMOS chips atop each other, sticking them together with dielectric glue and connecting the relevant parts with contacts called through-silicon vias (TSVs). As you might imagine, TSVs stick through the silicon substrate to whip information between short, stubby, vertical layers. According to one body of research, TSVs enable I/O power savings up to 98 percent.
So what material makes the best vias?
IBM looked at tungsten as a possible material. Others looked at graphene. But mainly everything seems to still rely on copper, the standard interconnect material, or a copper composite.
One of the issues raised by copper, however, is electromigration: as current flows through the wire, the metal atoms eventually migrate and form voids, and the wire breaks.
Hong Kong University rose to the challenge with a technology whose acronym hovers just a carbon molecule from disaster: Cu/CNT (copper/carbon nanotube) TSVs promise to retain all the conductivity of copper without the electromigration problem or the low melting point. Their results showed that "the EM lifetime of the Cu/CNT composite is more than 5 times longer" than copper alone.
The Next Problem
Even with the perfect interconnect, however, 3d chip stacking still poses a number of problems that need to be dealt with, before it will be possible to capitalize on even the best materials.
Depending on what you're stacking, you will run into different problems: logic on memory brings heat problems. (For DRAM, the upper temperature ceiling is 85 degrees C. For logic, however, the high temperatures often exceed 125 degrees.) Memory on logic brings different problems. They need to come up with some way of stacking them that protects different temperature areas. And I don't know what they're going to do about the heat sink.
The laundry list just keeps going: very thin dies will be used to stack memory to logic, and that requires a lot of grinding. DRAM bit cell retention can be adversely impacted by the thinning and package process.
And that brings us back to Conan
The most important issue is the connection between the stack; the reliability of connections is particularly important between memory and logic. Lining up these complex CMOS mash-ups is going to be as tough as getting that perfect right angle, and the punishment for low die yield is probably understated in the Stackenblocken bit.