After a hard slog, extreme ultraviolet (EUV) lithography seems to be closing in on a long-sought quarry: a light source bright enough to pattern chips cheaply and keep Moore’s Law marching along.
The technology, which uses 13.5-nanometer light instead of today’s 193-nanometer light, could—at least in the short term—allow chipmakers to create finer features without having to expose chips multiple times, a process that can add significantly to the expense of the manufacturing process.
But for years, EUV’s prospects were limited by the dimness of its light source. Unlike conventional lithography, which uses an ultraviolet laser, EUV generates its invisible light—just at the edge of the x-ray part of the spectrum—by turning tin into a plasma. ASML, which is developing EUV machines for the semiconductor industry, has put its support behind a particular approach called laser-produced plasma, which creates light by shooting 50,000 microscopic molten tin droplets per second across a vacuum chamber and vaporizing each one with a pulse of CO2 laser light.
At the SPIE Advanced Lithography conference in San Jose last week, ASML said it has pushed the limit of that light source to 200 W and aims to reach 250 W by the end of the year.
The company has long targeted 250 watts as the brightness needed for chipmakers to adopt the technology for high-volume production (the brighter the light source, the less time it needs to pattern a chip). This isn’t the first time that ASML has made a prediction about reaching that target; at one point, for example, the company expected to reach that goal in 2013. By that year, the goal still seemed far away; at the same SPIE conference in 2013, light source maker Cymer, which is now part of ASML, said it had pushed the brightness to just 55 W.
But Michael Lercel, ASML’s director of strategic marketing, says the situation is a bit different now: “I’m not going to try to pretend that we have everything solved, but 200 watts of power, scaling that to 250 watts, that’s not such a stretch.”
The dramatic progress comes thanks to an improvement in how effectively the tin is converted into a light-producing plasma. A big boost came with the addition of a “prepulse”—a low-intensity laser that flattens each tin droplet into a pancake shape so that more of its area is hit by the main, vaporizing laser. The basic approach isn’t all that new—Cymer presented early results on the prepulse approach in 2011. But thanks to a combination of modeling and experimentation, ASML has been optimizing the process. “The reason why the progress has been so dramatic in the last year—maybe year and a half—is understanding the physics of what’s happening in that process,” says Lercel. “It’s a lot of things that really are at the cutting edge of the plasma physics.”
The challenge going forward will be to get the machines to run at high power nearly all the time. A number of customers, including Intel and TSMC, are testing EUV tools at lower power in their fabs, and those “in the field” machines are producing wafers 70 to 80 percent of the time. But that’s still short of the performance of today’s 193-nm machines, which aim for 95 percent availability, 24-7.
Still, the attitude toward EUV seems to be shifting. “If you came here two years ago it was a fairly gloomy attitude. It’s changed quite a bit in the last year or two,” says Greg McIntyre, director of advanced patterning at the semiconductor research firm Imec, which is testing an ASML machine. The ramp in source power, he says, has been a stimulus to work on other pieces of the puzzle that will determine EUV’s success.
That list includes a number of other components in the lithographic process: masks that carry the patterns to be printed on a wafer; protective “pellicles” that guard those masks against contamination; and the photo-sensitive resists that the light must ultimately shine on and chemically transform in order to transfer a pattern to a wafer.
The big question is how—and when—all the pieces will come together. ASML says EUV machines could be part of high-volume chip manufacturing around 2018. TSMC, for one, says it plans to “exercise” the technology at the 7-nanometer node, which is set for that time. (A node is a now-vague indicator of a manufacturing generation, with smaller numbers corresponding to smaller features and higher transistor densities.) The company anticipates adopting EUV for high-volume manufacturing at the 5-nanometer node, which would happen around 2020.
But further delays could scuttle the chance that EUV will be used at all, says lithography expert Chris Mack. There are only so many nodes left: in addition to the expense and difficulty of manufacturing advanced chips, transistors and the ultrafine metal lines that connect them are bumping up against fundamental physical limits. “Time is the enemy of EUV,” Mack says. “There’s a closing window of opportunity, and since progress continues to lag there’s a real possiblity that EUV won’t be ready in time for anybody to use it in manufacturing.”
Still even Mack, an inveterate EUV skeptic who once wagered his Lotus Elise sports car against the technology, says he now harbors a “glimmer of hope” for it. The cadence of Moore’s Law, which once moved forward every two years like clockwork, seems to be slowing down. “There’s a real possibility that this slowdown in Moore’s Law could enable EUV to have enough time to catch up,” he says. “EUV was supposed to save Moore’s Law, but it could be the death of Moore’s Law could save EUV.”
Follow Rachel Courtland on Twitter at @rcourt.