Intel Interview: Getting Beyond "Darn Good" Devices

For at least a few years, the 3-D transistor was hiding in plain sight. Intel CEO Paul Otellini held up a shiny wafer full of them when he showed off the company's 22nm SRAM at the Intel Developer Forum in San Francisco in 2009. But it took until May this year before Intel revealed exactly how those SRAM transistors are different from their 32nm progenitors. Unlike the traditional planar transistor, which contains a gate spread along one side of a flat channel, Intel's Tri-Gate (or FinFET) transistor employs a gate that is draped over three sides of a 3-D channel, which juts out of plane like a fin.

The new transistors are smaller, faster, and consume less power. But, as Khaled Ahmed and Klaus Schuegraf of Applied Materials explain in the November IEEE Spectrum feature Transistor Wars, switching to FinFETs isn't the only way to keep boosting transistor density.

At this year’s Intel Developer Forum, I caught up with Intel Senior Fellow Mark Bohr to ask him how Intel settled on the design and why the company didn’t decide to go with the 3-D transistor’s most mature competitor, planar transistors built on wafers that contain a thin layer of silicon on top of insulating material (those transistors go by two names: fully depleted silicon-on-insulator and ultrathin body silicon-on-insulator).

Bohr says Intel had little choice but to go 3-D. Intel’s 32nm transistors, he says, are “darn good devices”, and switching to a 3-D architecture was the best way to continue improving power consumption and performance while packing more transistors on a chip. Intel has now put these 3-D transistors into production, and Bohr reckons the company is a good four years ahead of its competitors. Whether the rest of the chip industry will follow Intel's lead into the third dimension remains to be seen.

(Image: Intel)

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