Quantifying the Risk of Damage to Integrated Circuits in Space

Illustration: Victor Habbick/Getty Images

The dangers that electronics face in space from energetic charged particles emitted by the sun are pretty big. How big? Glad you asked. A researcher at Boeing has developed new computer-aided design software designed to help quantify the risk space weather can pose.

The perils related to geomagnetic storms were made painfully clear in 1989 when such a storm blacked out the entire Canadian province of Quebec within seconds. It left six million customers in the dark for nine hours, damaging transformers as far away as New Jersey, and nearly taking down U.S. power grids from the mid-Atlantic through the Pacific Northwest. Moreover, geomagnetic storms 10 times as strong are possible. One such event was the 1859 solar superstorm.

The risk of damage to electronics from space weather is even greater for satellites in orbit and spacecraft dispatched to other planets—areas far outside Earth's protective envelope. Designing circuits for use in space has to account for such dangers, but quantifying this risk has proven difficult.

Now William Atkinson at Boeing has developed software known as TSAREME (short for Total Space and Atmospheric Radiation Effects on Microelectronics) to account for errors induced by the impact of radiation in near-Earth orbits and inside the atmosphere. Atkinson will describe his invention in detail on 12 April at a meeting of the American Physical Society in Baltimore.

For electronics meant to be used in space, TSAREME computes the effects of strikes by protons, alpha particles, and other high-energy particles made of elements as heavy as iron. Inside the atmosphere, TSAREME models the effects of charged particles interacting with air molecules. That allows the software to account for how the magnetosphere, the bubble of plasma around Earth controlled by the planet's magnetic field, can vary with latitude.

The software analyzed satellite measurements of solar flares over a four-year period to test a variety of electronic designs with feature sizes varying from 1 micrometer down to to 15 nanometers. It found that there are a number of alternatives to conventional CMOS ICs that significantly reduce the risk of electronic disruptions in space. Among these are silicon germanium, silicon-on-insulator, and silicon-on-sapphire technologies. 

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