Tag Results for IEDM (11)

  1. IEDM: 3d Stackenblocken

    Actual footage of Intel's D1D production/development fab This Conan skit explains not just what chipmakers are trying to do about the interchip communication problem, but also the problem that plagues the solution. First: what is 3-d chip stacking and why would you do it? Stacking layers of integrated circuits atop each other is a solution to interchip communication problems detailed in a recent Spectrum article on multicore's very bad, no good, terrible day. At the heart of the trouble is the so-called memory wallâ''the growing disparity between how fast …

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  2. The 32-nm middle child

    Intel's done it. According to Intel's roadmap, the first 32-nm chips will roll out in devices in late 2009. By now, 32-nm test chips put the node squarely in the development part of Intel's three-year research-development-manufacturing cycle. TSMC did it in late September/early October, announcing two different 28 nanometer chip making processes slated for fabrication in 2010. IMEC did it and told us how at IEDM (immersion lithography). The notable odd man out is AMD, which just released Shanghai in November, debuting its hot new 45-nm chip technology just in time to mark the one-year anniversary …

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  3. IEDM Roundup, part 1

    At this year's International Electron Devices Meeting in San Francisco, the phrase of the day was 22nm CMOS. Because it is the smallest manufacturable feature of a transistor, and because those transistors have been getting inexorably smaller for the past 40 years, the technology node is the defining characteristic of microchips. I was under the impression that fabrication had barely started on integrated circuits at the 45-nanometer node, which represents the current state of the art. But though I have heard precious little about 32 this year, 22nm invaded the territory before 2008 was even out. 32 nm, in …

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