Printing III-V Transistors Onto Silicon

Engineers use a rubber stamp to get silicon and compound semiconductors to cooperate

Illustration: University of California at Berkeley

Crack, Peel, Stamp: Indium arsenide nanoribbons are formed on a compound semiconductor substrate by patterning with plastic (PMMA) and etching away excess material. A special rubber stamp then peels them away from the surface and deposits them on an oxide coated silicon wafer.

11 November 2010—Researchers have been trying for years to grow circuits made from compound semiconductors—known for their high frequency and light-emitting capabilities—on silicon with little success. The techniques were complicated and often resulted in defects. Even under the best circumstances, the resulting transistors were plagued by current leakage at the junctures where the two types of material met, which reduced the transistors’ efficiency. But a group of researchers in the United States and Taiwan, reported this week in Nature that they have hit upon a relatively simple way to integrate compound semiconductors and silicon with none of these drawbacks.

The team created high-performance nanometer-scale transistors using a pick-and-place printing process that puts indium arsenide nanoribbons on a silicon–silicon dioxide substrate in a way that is likely to deliver high yields and throughput. Though the technique itself isn’t new, this is the first time it has been shown to reliably print working nanometer-scale compound semiconductor devices on silicon.

The researchers began by growing an 18-nanometer-thick layer of indium arsenide on a substrate consisting of a layer of aluminum gallium antimonide atop a layer of gallium antimonide. That narrowness is important, points out John Rogers, a University of Illinois materials scientist who developed the transfer printing technique but was not involved in the research reported this week. Electrons in semiconductors with thicknesses below about 50 nm behave as if they are moving through a two-dimensional object instead of a three-dimensional one, and that makes for more efficient transistors.

The group, which was led by Ali Javey, a materials scientist at the University of California, Berkeley, then used photolithography to etch the sheet into 300-nm-wide ribbons. Then they etched away the aluminum gallium antimonide layer with chemicals, leaving the ribbons attached to the substrate with just the slightest bit of material. The suction provided by a specially made rubber ”stamp” pulled the ribbons away from the substrate, and then the ribbons were deposited on a wafer of silicon.

Using the same process, the researchers were able to add an array of 48-nm-thick ribbons perpendicular to the first array. By laying down nickel contacts atop the nanoribbons, they formed functioning transistors.

The team also solved another problem that had bedeviled researchers, namely the incompatible atomic interfaces between indium arsenide and silicon dioxide. They simply heated the indium arsenide, transforming a precise amount of the semiconductor into a dense layer of indium arsenic oxide that had few of the dangling bonds that result in current-leaking voids at the juncture where the two materials meet.

Rogers says they have demonstrated "what looks to be a realistic manufacturing technique for performance-enhanced silicon logic components at unprecedented regimes of thickness."

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