Choosing the right metal
By far the biggest challenge in bringing metal gates into production is figuring out which metals to use. Several factors are at play, says Wong: the materials and their combinations, thermal stability, and reactions with the underlying insulating oxide. To give the transistor the desired threshold voltage, the metal must also have the right work function, which is the term for the energy needed to extract an electron from the metal into a vacuum. Put another way, it is a measure of how strongly electrons are attracted by a metal. The amount of voltage that you have to apply to the gate to attract electrons into the channel depends on that work function.
To complicate matters further, NMOS and PMOS transistors would require gate materials with different work functions: smaller for NMOS and larger for PMOS. Today, researchers are exploring tungsten and molybdenum, among other metals. The use of a ruthenium-tantalum alloy was proposed as a possible gate material in a paper presented at the 2001 IEEE International Electron Devices Meeting held in December (Washington, D.C.), by Huicai Zhong, then studying at North Carolina State University in Raleigh. The beauty of this approach is that the work function can be adjusted by changing the ruthenium-tantalum mix to set the required threshold voltage of the transistor.
The end of the planar road?
The use of high-k dielectrics, plus metal gates, plus strained silicon, plus increasingly complex doping profiles will extend the life of the planar CMOS transistor for at least another decade. But then what? Researchers are looking to double-gate transistors to take over when planar CMOS finally runs out of steam. In double-gate devices, the gate is on both sides of the channel, giving much tighter control of the transistor's on and off states.
"There are in general three ways to build double-gate devices," explained IBM's Wong. "You can do it horizontally with one gate on top and another on the bottom. You can do it vertically so that the current runs perpendicular to the silicon surface, or you can do it with the channel and gate perpendicular to the surface but with the current parallel to the surface." The last approach is called a FinFET and is the front-runner in the double-gate device race. The approach is under development at IBM, AMD, Intel, and Hitachi, along with others in the semiconductor industry, according to Jeffrey Bokor, professor of electrical engineering and computer science at the University of California at Berkeley.
The device is built by thinning the silicon layer of an SOI wafer down to a few tens of nanometers, then etching it to form a narrow vertical fin that sticks up from the wafer surface. The fin, which rests on the insulator, forms the channel of the device. Source and drain electrodes are built at each end of the fin and the gate drapes over both of its sides. Work on FinFETs has been going on for some years, but the impending end of the road for planar CMOS has researchers redoubling their efforts to perfect the device. At last December's International Electron Devices Meeting, IBM presented results on a FinFET that performed every bit as well as a conventional transistor.
One advantage of the FinFET, according to Berkeley's Bokor, is that the channel is undoped. That feature will become increasingly important as the channel length shrinks. The number of dopants in doped channels becomes exceedingly small as their length shrinks to only a few tens of nanometers. Consequently, fluctuations in this number during manufacture, along with small variations in the channel length across the chip, could wreak havoc on threshold voltages, degrading--if not ruining--circuit operation. In contrast, the absence of channel doping allows the gate to have much more influence over the device's threshold voltage.
Another advantage is that the fin can be made extremely thin. This feature means that no region of the fin escapes the influence of the gate. Power consumption is lower because there is no leakage path for charge carriers to flow along between the source and drain when the device is off.
Multiple-gate transistors may not stop at two. As we go to press, Intel researchers are preparing to describe a triple-gate transistor, also based on a silicon fin, at the International Solid State Devices and Materials Conference to be held 17-19 September (Nagoya, Japan).
In with the new
As for double-gate devices, Bin Yu, senior researcher at Advanced Micro Devices Inc. (Sunnyvale, Calif.), says their use will depend on the IC. "AMD is in the high-performance microprocessor business and will try to push planar CMOS to the limit," he told Spectrum. "But those making low-power chips--like Motorola, for example--may well use double-gate devices first, because of their incomparable ability to control current leakages, which is important for handheld products."
Other factors in addition to short channel effects and device leakages must be dealt with as well, Yu continues. With narrower linewidths and smaller source and drain junctions, the resistance in series with the transistor's channel will increase, driving up power consumption and degrading performance. With many more transistors running at much higher frequencies, IC power consumption will also rise. The amount of heat that transistors can tolerate during the manufacturing process will go down, making it more difficult to dope them effectively. Then there's manufacturability. "Can we still manufacture so many transistors on a chip with good enough uniformity of electrical performance?" Yu asks.
Engineers will likely solve these problems and others as semiconductor technology progresses through the technology nodes. And when CMOS transistors, planar or otherwise, can no longer be scaled down, more exotic devices like nanotubes, single-electron transistors, superconducting transistors, and molecular transistors will be vying to take their place.