24 February 2005--The old-fashioned way to speed up circuits was to shrink the components, but now that the payoff from that strategy is declining, semiconductor manufacturers are seeking other ways to squeeze out performance--notably by squeezing the semiconductor itself. If you squash or stretch certain semiconducting crystals, they convey electrical charges faster. In a CMOS transistor, the result of such "strain" is faster switching and higher current output, with most of the effect coming in the channel--the connection between the transistor's source and the drain. In the past two years, strained-silicon channels, in which the silicon is stretched, have come into general production. Now scientists at IBM Corp. have demonstrated still greater improvements in channels made of germanium that has been squeezed, or compressively strained.
According to Huiling Shang, a research staff member at the IBM Thomas J. Watson Research Center in Yorktown Heights, N.Y., transistors with strained-silicon channels offer output current just 10 to 30 percent higher than that in unstrained silicon, whereas strained-germanium channels raise it by 200 percent. She notes that although the idea had been kicking around for a few years, it became practical only when IBM discovered a fabrication method compatible with conventional CMOS technology, the linchpin of the electronics industry. The company announced the discovery in December, at the International Electron Devices Meeting, in San Francisco.
In its new method, IBM starts with a substrate crystal made of silicon atoms salted with some germanium atoms. The germanium atoms' larger size makes the hybrid crystal bigger than one of plain silicon, but not as big as one made of pure germanium. That way, when the researchers grow a thin layer of pure germanium on top, the two crystals fit together like an egg-crate crammed into the sockets of a smaller crate. The larger crate--here, the grown layer of pure germanium--gets squeezed tight, to form strained germanium.
IBM's first goal is to build strained germanium channels into the slower of the two kinds of transistor that make up a CMOS device: the p-type, in which electron vacancies, called holes, carry the current. (In the other kind, the n-type transistor, the electrons in strained silicon channels move so much faster than they do in ordinary unstrained channels that strained silicon suffices, at least for now.)
To make the channels on p-type transistors, the researchers isolate a construction site on the silicon-germanium substrate by etching shallow trenches and filling them with silicon dioxide, an insulator. Then they lay down a protective coating on all but the isolated region. Next they deposit germanium atoms on the exposed area, forming strained germanium.
On top of the germanium they lay down a very thin layer of silicon, which they oxidize to provide insulation between the channel and the soon-to-be-formed gate. They follow this procedure by stripping off the protective coating. From this point on, fabrication proceeds along the standard CMOS manufacturing steps--the oxidation of silicon to make the gate insulation, the building of a gate on top of the oxide, and the wiring of the transistors to link them into circuits.
The key to IBM's success was finding a way to oxidize the top layer of silicon at 400 0C, some 200 degrees cooler than usual. This trick made it possible to finish the transistor without relaxing the strain that had been so laboriously induced in the germanium channel.
Shang and her colleagues also built transistors with hafnium dioxide as the gate insulation. This material has the advantage of minimizing current leakage through the very thin gate-to-channel gap, a problem that gets worse as transistors get smaller. The major drawback of hafnium dioxide had been its tendency to raise threshold voltage--the voltage needed to turn the transistor on. But that's no problem in Shang's devices.
She says that though the technology is still in development, it could well make it into manufacturing in the coming decade, as circuit wire widths shrink to 32 nm and below.