7 December 2011—After years of doping, straining, shrinking, and tweaking, engineers seem to have exhausted all their strategies for improving the planar complementary metal-oxide semiconductor (CMOS) transistors at the heart of today’s computer processors. Producers of cutting-edge chips are now resorting to new structures—building up in three dimensions or constructing transistors in ultrathin layers of silicon—to ensure that devices keep shrinking and that Moore’s Law keeps going just a bit longer.
But semiconductor start-up SuVolta is betting that the traditional planar structure still has some life in it and that it can go toe-to-toe with the new alternative designs. The firm hopes to build a business licensing a technology it says will reduce power consumption and boost performance with minimal changes to the way transistors are made.
When the Los Gatos, Calif.–based company emerged from stealth mode in June, it gave few details on exactly how this could be accomplished. But the firm is now ready to unveil the basics of the approach this week at the 2011 IEEE International Electron Devices Meeting, in Washington, D.C.
The trouble with planar transistors is twofold: When you try to make them smaller, they leak current and waste power. Just as troubling is that the more you shrink them, the harder it gets to make them uniform enough for one transistor to behave the same as the next.
To some extent, both problems are caused by unavoidable variations in the number of dopant atoms in the silicon. Silicon is traditionally doped with elements like boron or phosphorus in order to create and fine-tune the energy barriers that both block and permit current to flow. Electric fields are used to steer streams of dopants into the silicon.
But as chipmakers have reduced the size of CMOS transistors, the total number of dopant atoms in a key part of the transistor, the channel, gets smaller. The channel is used to carry current between the source and the drain, and it’s controlled by a gate that is typically mounted on top of the channel. The fewer dopants there are, the stronger the influence of random fluctuations in the dopant concentration. These fluctuations have come to have a strong impact on a transistor’s electronic properties, resulting in a high proportion of less-than-ideal transistors that leak more power or switch slower than designed.
SuVolta hopes to make transistors less leaky and more predictable by changing the way their channel regions are doped. Instead of evenly doping a transistor channel, the company’s strategy is to lay down the channel in three layers, each about 50 to 100 angstroms thick, and each with a different concentration of dopant.
Under the influence of the gate’s voltage, current moves primarily through the topmost layer of silicon, which contains no dopants at all. The bottom layer in SuVolta’s transistor is made up of heavily doped silicon, which provides a reservoir of dopant atoms. The reservoir shields the electric field induced by the transistor gate, preventing it from penetrating deeper into the silicon, where it could create a path for current to leak across.
In between the undoped and heavily doped layers of the channel, SuVolta’s design calls for a layer with an intermediate concentration of dopants. By altering the concentration of dopants in this middle layer, SuVolta can fine-tune a transistor’s threshold voltage—the amount of voltage at the gate needed to turn the transistor on or off.