New Lithography Makes Smallest SRAM Yet

A radically different chipmaking process could pave the way for future generations of microprocessors

Image: University of California, Berkeley

30 November 2009 A new type of lithography, which uses an electron beam to spark a chemical reaction, could provide a cheaper way to build the incredibly tiny transistors that the chipmaking industry will require in a few years. Researchers from Taiwan and the University of California, Berkeley, say they've made static random access memory (SRAM) that anticipates 16-nanometer chip features with a new process called nano injection lithography.

Hou-Yu Chen and his colleagues from National Nano Device Laboratories, in Taiwan, will present their work next month at the International Electron Devices Meeting (IEDM) in Baltimore. They say their technique may provide an alternative to lithography that relies on extreme ultraviolet light (EUV), which still is beset by problems and could be extremely expensive.

"This is the smallest SRAM made," says Chenming Hu, a professor of microelectronics at UC Berkeley and a coauthor of the paper. "There are a lot of concerns about the scalability of SRAM going forward."

The device the team made was a six-transistor SRAM in a 0.039µm2 cell. The previous record holder was based on 22-nm features in a 0.1 µm2 cell.

SRAM occupies an ever-increasing percentage of a chip, taking up as much as 80 percent of cell area in some designs, Hu notes. "The size of the SRAM cell becomes critical to the cost of the chip, so SRAM is always the most taxing circuit for testing process capability," he says. Shrinking the SRAM, in other words, is key to shrinking the chip's circuitry as a whole.

Standard lithography uses a set of masks to create a pattern of structures in a photoresist that's exposed to ultraviolet light. The Taiwan team's process eliminates both the masks and the photoresist, relying instead on a metallorganic gas, an organic molecule studded with atoms of platinum. An electron beam with a diameter of 4.6 nm is fired at the gas, causing a chemical reaction that deposits the platinum on the silicon chip in the desired pattern, while the rest of the gas flows away. With this hard mask deposited on the silicon, the researchers then use chemicals to etch away exposed silicon and thereby create the desired circuits. The platinum mask is then chemically removed.

Eliminating the masks and the photoresist cuts the patterning process from five steps to one, greatly simplifying production. The researchers say that EUV masks are projected to cost around US $3 million a set and the EUV lithography machines about $60 million apiece. So the nano injection lithography could also be significantly cheaper. Hu says the technique also allows for finer lines and closer spacing than typical electron-beam lithography.

The team built its SRAM based on the nanowire structure known as a FinFET, a field-effect transistor shaped like the fin on a fish's back that protrudes vertically from the silicon. Hu, who invented the FinFET, says the shape is important when the dimensions are so small, because a gate dielectric can be applied to the entire periphery of the fin, preventing the current leakage that troubles small transistors.

The process, of course, could be used to build other circuits on a chip besides SRAM. Hu says the work is in a fairly early stage and needs to be developed further before researchers know if it can be applied to full-scale chip manufacturing for a reasonable cost. One major concern is that the process provides relatively low throughput. The researchers say their technique is mainly an alternative for EUV and e-beam lithography for low-volume fabrication.

"It seems this new nano-injection-lithography technique may indeed be of interest for exploring 16-nm node device dimensions," says Anabela Veloso, who specializes in CMOS devices and technology at IMEC, an independent research center for nano-electronics in Belgium. "However, as an electron-beam based technique, and without further information on potential throughput and [alignment of different patterns], the feasibility of its application for volume production seems very unlikely."

Skepticism aside, the researchers will explore other ways to improve the technique, such as using other gases. They used a gas that was readily available and worked, but may not be the best for their purposes.

When the 16-nm chip is coming is not certain, although Hu says some optimists expect it by 2013. "The hope is to have [this process] ready by then, but a lot more work is needed," he says.

About the Author

Neil Savage writes about technology from Lowell, Mass. He recently reported on another development from IEDM—stackable phase-change memory

This story was corrected on 2 December 2009.

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