First Gallium-Based FinFETs
Purdue researchers take compound semiconductors into the third dimension
23 November 2009—Silicon researchers envision that future generations of transistors will evolve from the flat structures they are now to three-dimensional devices called FinFETs, where two or more narrow fins are the critical features. Now research into better-performing—but more-expensive—compound semiconductors has caught up. Engineers at Purdue University’s Birck Nanotechnology Center have created the first FinFETs, or fin-shaped field-effect transistors, made of a compound semiconductor called indium gallium arsenide (InGaAs). If such devices can be integrated into complex circuits, they could improve cellphone communication and make for chips that compute faster.
Compound semiconductors, the stuff of high-frequency circuits and optoelectronics, are among the leading contenders to replace silicon in electronic circuits when Moore’s Law runs out of steam. They make transistors that switch faster and more efficiently, which could solve some of the big problems facing future generations of silicon integrated circuits. But they have even more trouble than silicon when shrunk to the tiny sizes of today’s transistors: Mainly, they leak.
Smaller transistors, silicon or otherwise, tend to dribble current even when switched off, wasting power. They also tend to switch between “off” and “on” less efficiently when shrunk. Such effects related to transistor size are called short-channel effects, referring to the shortened channel between the source and the drain through which current flows under the control of the gate. They’re a “showstopper” for scaling down transistors, says former IBM engineer Yuan Xie, who is now an associate professor in the department of computer science and engineering at Pennsylvania State University.
To solve short-channel effects in silicon, engineers have experimented with replacing the flat, or planar, structure that allows the transistor gate to control the electron channel only from one direction—the top—with a pair of 3-D fins. The technique hasn’t gone mainstream yet, Xie says, because “people say, ‘As long as I can do scaling, why go for a new technology?’ ” But as transistor scaling reaches its limits, alternatives like FinFETs could be “the next big thing,” he says.
FinFETs are useful, says Purdue electrical and computer engineering associate professor Peide Ye, because they give three control surfaces, “not just from the top, but also from the neck.”
Now Ye’s group has combined low-leakage FinFET technology with the fast-switching capability of compound semiconductors to see if they can make a silicon-beating transistor.
At next month’s IEEE International Electron Devices Meeting, Ye’s group will report the creation of InGaAs FinFETs. The research shows that these FinFETs—with fins ranging from 100 nanometers to 200 nm in length—leaked less current and reduced other short-channel effects compared with ordinary InGaAs devices.
That’s useful, because short-channel effects such as current leakage are even more pronounced for III-V semiconductors like gallium arsenide (so called because they’re made from elements in the third and fifth columns of the right side of the periodic table).
The 3-D fin structure should also help device performance by pushing through more current during the transistor’s ”on” state, says Ye, because the sides of the fins become additional channels for electrons to flow through. That’s particularly important for III-V transistors, where boosting current has been a hurdle.
“That’s the beauty of the FinFET,” says Ye. “It’s more challenging in terms of manufacturing, but you could get much better on-state and off-state performance.”
Key to the construction of InGaAs FinFETs was the use of a technique called atomic layer deposition (ALD).
This process allowed the researchers to grow an insulating film of aluminum oxide over the transistor fins, in multiple layers, each just one atom thick. So for their 5-nm aluminum oxide insulating layer, the researchers put down 50 one-atom-thick layers of aluminum oxide at a time. This technique was not used in CMOS manufacturing until recently, when Intel employed it to lay down high-k dielectrics in the company’s latest generations of chips.
ALD is uniquely suited to the FinFET structure, Ye says, because it’s a chemical bonding process where the researchers can control the surface very precisely and form an even layer of insulator all the way around the fins. Alternatives, such as a physical vapor deposition process, would mostly just “hit the top” of the structure, Ye says.
ALD, combined with their special etching techniques, gives the Purdue team a III-V equivalent to the silicon FinFET, according to Yanqing Wu, who led much of the research in Ye’s lab (and successfully defended his dissertation two weeks ago). That gives hope for a “fab friendly” process that could take advantage of already existing technology in chip-manufacturing plants, rather than requiring expensive new equipment, he says.
“All atomic layer deposition, FinFET, and III-V can be done easily with the available manufacturing infrastructure,” Ye says.
Their goal will be to use this process to continue to shrink down transistors while defeating the short-channel effects that plague traditional silicon transistors and III-V devices.
Wu says that this work is important because “you have to solve short-channel effects to even study shorter gate lengths.” Now that they’ve shown it’s possible to improve performance with FinFETs and ALD-grown insulators, this “paves the way to further scale into gate lengths of less than 100 nm” with III-V FinFETs, Wu says.
Although they’ve shown that “the physics principle works,” says Ye, it will still take much more engineering to get the process into CPUs or cellphones.
It has been shown that individual III-V devices perform better than silicon devices, according to Wu. But combining many devices into an integrated circuit is the key. “If that can be demonstrated, then we can at least partially replace silicon by III-V in the CPU,” Wu says.