Intel’s 3-D leap was anticipated, but its timing still came as a surprise. “Moving the technology from the lab to the fab is a big deal,” says Tom Halfhill, a senior analyst at the Linley Group, in Mountain View, Calif. Based on available road maps, Halfhill says, other chipmakers working on FinFETs are a good four to five years behind Intel. “As far as we know, nobody else is close to volume production,” he says.
Intel’s FinFET isn’t the only foray out of Flatland. In 2012 there will be solid progress on an even more promising trick: stacking chips and wiring them together with interconnects that run straight down the stack, like elevator shafts in a skyscraper. If all goes well, this reworked interconnect technology could yield vastly faster and more efficient devices, no matter how chunky their transistors might be.
In some ways, 3-D is nothing new to chipmakers. Flash memory, for example, is stacked to cut down on volume and boost speed. But chip stacking has been limited by wiring problems. Today’s interconnects don’t run through the silicon itself but instead go millimeters around it, impeding speedy signaling and sapping power along the way. Horizontal real estate is also precious. The thinnest interconnects are still 25 micrometers wide, and they must be packed along the edges of a chip, putting strict limits on how many input/output connections any one chip can handle.
Thus the attractiveness of going vertical, connecting one chip to another with copper lines that go straight through the silicon. If chipmakers can cheaply manufacture these through-silicon vias (TSVs), they can pack many more connections side by side using much slimmer wires. Going through chips instead of around the side will also reduce the length of interconnects from millimeters to 50 μm or even less—as thin as individual wafers can be made. The potential advantages are huge. Samsung, one of several companies working on making dynamic RAM memory stacks connected by TSVs, has estimated that the switch to vertical interconnects will cut power consumption in half, increase bandwidth by a factor of eight, and shrink memory stacks by some 35 percent.
“It’s really phenomenal that you can do something like that,” says Sitaram Arkalgud, who directs the 3-D interconnect program at Sematech, a semiconductor industry consortium. “It’s not often that you see this kind of a revolution come along.”
To build TSVs, a wafer maker has to etch deep, narrow holes into a silicon wafer and then fill them with a nearly flawless layer of insulating material and then copper. But as a wafer heats up, copper expands at more than five times the rate that silicon does, exerting stress that can crack the wafer and render it useless.
Shepherding these wafers through the chip manufacturing process is also a challenge. Each wafer must be thinned to roughly 50 μm, less than the thickness of a human hair. Wafers that thin can curl up like pencil shavings. To work with them, chipmakers have to temporarily attach them to plates that can stabilize them during processing.
But industry watchers say that most of the main technical hurdles have now been overcome. This year, companies will be working out ways to introduce TSVs without adding significantly to the cost of making a chip. This is “the year we figure out how to make them manufacturable. It’s the year of process development and yield improvement,” says industry consultant E. Jan Vardaman, president of TechSearch International, in Austin, Texas.
In fact, the most dramatic achievement in the coming year might be a simple stacking configuration that’s often called 2.5D. This approach takes advantage of TSVs by running them through an intermediate layer of silicon called an interposer, which sits between an IC and a PC board. By one measure, the technology is more or less two-dimensional. All the packages you choose to put in a device—RF receivers, graphics units, memory, logic—still sit on the plane of the motherboard. But instead of copper traces running across the motherboard from package to package, in this configuration copper connections run through TSVs and past the interposer layer, where the vertical wiring is connected in a series of horizontal patterned layers. By moving all the connections outside the plane, device makers can place chips right next to one another, saving space and power.
One of the pioneers of interposer technology is Xilinx, in San Jose, Calif., which has used TSVs to wire together four field-programmable gate arrays to form the world’s largest FPGA. This programmable pachyderm contains nearly 7 billion transistors, easily 50 percent more than the biggest single FPGA, Xilinx says. The firm estimates that the device consumes less than a fifth of the power that would be needed to operate a comparable set of individually packaged FPGAs strung together with traditional copper interconnects.