Design Challenges Loom for 3-D Chips

Through-silicon vias promise smaller, smarter chips--but not yet

Photo: Imec

Columns of Copper: Through-silicon vias connect multiple silicon dies stacked vertically in a single chip. These test TSVs are spaced 10 micrometers apart, insulated by thin layers of silicon dioxide.

17 February 2010—Three-dimensional microchip designs are making their way to market to help pack more transistors on a chip as traditional scaling slows down. By stacking logic chips on top of one another other or combining logic chips with memory or RF with logic, chipmakers hope to sidestep Moore's Law, increasing the functionality of smartphones and other gadgets not by shrinking a chip's transistors but the distance between them.

"There's a big demand for smaller packages in the consumer market, especially for the footprint of a mobile phone, or for improving the memory bandwidth of your GPU," says Pol Marchal, a principal scientist of 3-D integration at European microelectronics R&D center Imec.

On 9 February, at the IEEE International Solid-State Circuits Conference (ISSCC), in San Francisco, Imec engineers presented some key design challenges facing 3-D chips made by stacking layers of silicon circuits using vertical copper interconnects called through-silicon vias (TSVs). These design constraints will have to be dealt with before TSVs can be widely used in advanced microchip architectures, Marchal says.

Among other uses, TSVs can increase the bandwidth between logic and memory. Connecting dynamic RAM to logic circuits through traditional wire interconnects takes up space and limits bandwidth, which in turn limits processing speed. Data must be bundled onto a few interconnects at one end and unbundled at the other. That consumes a lot of power and increases latency, creating a bandwidth bottleneck.

TSVs could remove the bottleneck, Marchal says, because they can be placed closer together than the typical 200 micrometers that separate input/output pins. Imec's research has demonstrated TSVs placed just 10 µm apart, though Marchal says that the most likely widespread early adopters of TSVs would probably space them about 50 µm apart, which improves the yield from the bonding process.

The question, according to Marchal, is whether engineers will be able to design chips that use those vertical interconnects to maximum advantage.

The first challenge is size. Products available today that contain TSVs, such as some image sensors and DRAM stacks, use relatively hefty chunks of metal—about 100 µm or more in diameter. But that's not good for integrating disparate types of devices, such as logic and memory, because the TSVs themselves take up too much space on the chip. Imec's work has demonstrated TSVs just 5 µm in diameter, which allows for squeezing more TSVs—and transistors—on each layer.

Heat is another problem for TSVs. Imec's research shows that thermal characteristics are three times as important for 3-D structures as for 2-D ones, based on simulated results, because the thin wafers and poorly conductive adhesives holding them together don't spread heat evenly throughout the chip, creating hot spots. If DRAM circuits were to heat up too much during use, for example, they could corrupt data or cause other reliability issues. While these problems may be more important for high-performance applications than for low-power consumer gadgets, Marchal says, designing the chip's floor plan to take heat into account could prevent poor performance in low-power devices, too.

Another challenge is mechanical stress in the silicon around the TSV, because the copper TSVs contract faster when cooling than their silicon bedding does during processing. That stress can hinder transistor performance. Designers will have to take into account how much stress a system can handle and how far apart the TSVs should be to reduce stress in the silicon, depending on a device's application, Marchal says.

Photo: Imec

Also, the proximity of TSVs to transistors on the chip can alter performance values, such as threshold voltage and drive current. Designers will therefore have to introduce "keep out" areas on the chip—areas where there are no devices. An analog component, for example, must be tens of µm from a TSV in order to keep it from reducing performance more than 0.05 percent for devices made using the common 65-nanometer lithography process, Imec's research showed.

So 3-D chip designers will have to carefully balance the cost of the altered architecture that TSVs require with the benefit of tighter integration. Otherwise, chips with TSVs might turn out to be just as costly in terms of wasted space or poor performance as the multiple 2-D chips they are trying to replace. Imec is working with major electronic design automation companies to do such trade-off modeling.

In addition to design considerations, there are other important questions still to be answered on the processing end. For instance, it remains to be decided where the construction of TSV-based chips will be completed.

Foundries are responsible for adding TSVs to the wafers that will become the chip's layers, but not necessarily for thinning the wafers down and stacking them. According to Marchal, the chip industry wants packaging houses to take charge of thinning, stacking, and slicing and dicing to make the process cheaper. Of course, that would mean the capital expense of the needed manufacturing tools would come out of packagers' pockets.

But foundries don't want to relinquish their products before the job is technically complete, as doing so could incur liability for potential damage at the packaging house, Marchal points out. He says the question foundries ask is, Who gets the blame if something goes wrong?

However it shapes up, the decision will have to be made soon, Marchal says, because "the industry pull for this technology is big." TSVs are expected to widely populate chips by 2012 or 2013, he says, so he expects a decision this year.

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