We rely on our mobile devices for an almost comically long list of functions: talking, texting, Web surfing, navigating, listening to music, taking photos, watching and making videos. Already, smartphones monitor blood pressure, pulse rate, and oxygen concentration, and before long, they’ll be measuring and reporting air-pollutant concentrations and checking whether food is safe to eat.
And yet we don’t want bigger devices or decreased battery life; the latest Android phones, with their vivid 4.3-inch screens, are already stretching the definition of pocket size, to say nothing of the pockets themselves. The upshot is that the electronics inside the devices have to do more, but without getting any larger, using more power, or costing more.
Transistor density on state-of-the-art chips continues to double at regular intervals, in keeping with the semiconductor industry’s decades-old defining paradigm, Moore’s Law. Today there are chips with billions of transistors at a price per chip that has headed steadily down for decades. Innovations that pack more and more circuits onto a chip will indeed continue, as will the more recent trend of putting very different functions on a single chip—for example, a microprocessor with an RF signal generator.
If we want to teach our smartphones new tricks, however, we’ll have to do more than equip them with denser chips. What we will need more than ever are breakthroughs in an area not previously considered a major hub of innovation: the packaging of those chips. Packaging refers loosely to the conductors and other structures that interconnect the circuits, feed them with electric power, discharge their heat, and protect them from damage when dropped or otherwise jarred. But today, the drive to pack more functions into a small space and reduce their power requirements demands that chip packages do much more than they ever have before.
A packaged chip is a sort of puzzle, with certain fixed and well-defined pieces. Before we talk about how packaging designers are putting those pieces together in new ways, it will help to review the standard ones.
The astoundingly complex manufacturing process that leads to a chip starts with a wafer, a dinner-plate-size circle of a semiconductor material, typically silicon. Manufacturers etch, print, implant, and perform all sorts of other operations to turn a blank wafer into a grid of rectangles, each about the size of a fingernail and mind-bogglingly dense with transistors and interconnections. Sliced apart, those individual rectangles are what specialists call die. Properly packaged, each die becomes a chip. These days, many people use the terms chip and die interchangeably, but traditionally, the word die referred to a naked integrated circuit without packaging. We’ll stick to that traditional terminology here so that we can succinctly make it clear whether we mean a packaged chip or an unpackaged die.
Inside your smartphone, you don’t see naked die, of course. You see little plastic slabs of varying sizes, with scores of tiny metal prongs sticking out like insect legs, soldered onto a circuit board. The plastic slabs are the exterior of the packages. The fragile die are inside them, protected from damage during manufacture or use and connected to other chips through those prongs and the traces on the circuit boards.
These circuit boards are critical, of course, to any electronic system, but they don’t actually occupy all that much space inside those systems. In fact, if you open up a smartphone today, you’ll find that the amount of space allocated to electronics is rather small, so efficient use of that space is key.
Starting in the mid-1970s, designers trying to pack more functionality into a small space created systems on chips. What that means is that they designed digital and analog circuitry, memory, logic, communication, and power elements that were manufactured by a single process on a single die. This integration wasn’t easy, because the processes, materials, and technologies optimal for each of these functions tend to be very different. For example, a communication or analog chip might ideally use gallium arsenide as the substrate. It might be built in 180-nanometer technology, which basically means that the smallest features of the devices on that chip measure roughly 180 nm across. A digital processor chip, on the other hand, would use a silicon substrate with 32-nm technology. Power and noise considerations also vary tremendously; the analog chip might require a much higher voltage, and noise from the digital circuitry could interfere significantly with the performance of the analog sections.
The upshot is that integration of all those functions onto a single die requires compromises in every circuit type in order to use the same process and material, thus lowering performance and increasing power consumption. A process that works for multiple types of functions is optimal for none.