To see how the grid improves the manufacturing flow and the R&D process, let’s look at a 25-piece lot of experimental wafers—call it Lot X500. The wafers, coated with resist, are about to go into the stepper, where the mask patterns will be repeatedly projected onto them. There are dozens of steppers in each of our fabs. We’ll call this one Stepper No. 8.

First, the Manufacturing Execution System (MES) choreographs all the steps necessary to get Lot X500 through the next manufacturing step before anything is physically moved. The MES knows everything about the tens of thousands of wafers in the fab and all the machines that process them—how many steps each wafer has gone through and its location in the fab, for instance, or the health of each machine and whether or not it is busy.

The MES knows, for example, that Lot X500 has already passed through several process steps and is sitting in a front-opening unified pod, which is basically a kind of storage and transport container for batches of wafers. This pod is in a larger storage rack that contains thousands of such pods all arranged on floor-to-ceiling shelves, each identified by row and column location. The MES maps out where Lot X500 is and where it needs to go next—the stepper station. The MES then announces Lot X500’s virtual location on the software grid.

The Fab-Wide Scheduling module, which is constantly scanning the grid for updates on the thousands of pods being processed all over the fab, sees that Lot X500 is ready for photolithography and needs to be assigned to one of the many steppers on the manufacturing floor. The scheduler also recognizes that Lot X500 is destined to become Core 2 Quad microprocessors—Intel’s four-core microprocessors, which will be fabricated at 45 nm—and determines which stepper is available and qualified to do the job.

Just as the scheduling system is constantly scanning the grid to determine tool availability and wafer locations, the tools themselves are perpetually posting information about their readiness to the software grid. In this case, Stepper No. 8 signals its tool controller that it is idle and therefore ready to accept a new lot of silicon wafers. The controller, a program that is the tool’s interface to the grid, translates the tool’s message—“I’m idle”—from a form of machine language into XML and posts it to the grid. The scheduler sees this announcement and assigns Lot X500 to Stepper No. 8, a match it subsequently posts to the grid. Now it’s time for the virtual to become real.

The Material Handling and Tool Control sees the match of lot and stepper on the grid and assigns a robot to retrieve Lot X500 from its storage unit. That assigned robot places the pod on a carrier that zooms along an overhead monorail track at 5 meters per second to the stepper station. When Lot X500 arrives at Stepper No. 8’s port, the stepper’s controller puts a request on the grid asking for processing information for this specific lot. The Advanced Process Control module sees this request, calculates the optimal recipe settings to use, and provides the settings to the stepper’s controller.

The controller also takes readings from sensors monitoring the stepper’s health and posts that data on the grid. If Stepper No. 8 runs into trouble—say, an issue with the timing of an exposure—the Statistical Process Control software module crunches the data stream coming off the tool, identifies the problem, and publishes an alarm message on the grid. This alerts the Equipment Manager module to turn the machine off.

The Exception Notification system sees that Stepper No. 8 has gone down and pages maintenance personnel—actual human beings!—to come and investigate. Engineers are dispatched to inspect the lot and the machine. Once the machine is fixed, Stepper No. 8’s status is changed from “down” to “production ready.” Depending on the scheduler’s priorities, Lot X500 is moved back to storage or on to the next step.

After Lot X500 makes it through all the processing steps, the final chips are tested and the resulting data crunched by several analysis engines in the Engineering Analysis Framework suite. These analysis programs include ones that analyze the yield of working chips out of the total produced, and they also record such transistor-performance parameters as speed and power consumption. The programs correlate the yields and performance parameters to the recipes used on Lot X500 to identify desirable tweaks to the standard Core 2 recipe.

For instance, from the level of current it takes to turn a chip’s transistors on and off, we can decide whether the kind or amount of ions that we are implanting in the silicon at an early stage needs to be changed. Within a matter of minutes, the Advanced Process Control module can send the revised recipe to the implant tool so that all wafers entering that stage can take advantage of the optimal dosage of, say, arsenic ions.

Once the entire process has been proven to work in a technology development line creating experimental chips, it is exactly copied at the production fabs. That means we make our high-volume manufacturing lines look as much like the technology development line as physically possible so we can produce millions of chips with consistent quality. We use the same pipes to deliver the same chemicals and gases to the same tools, which are laid out in the same configuration. The AMT system ensures that the same recipes are used, and it compares data across all the sites to ensure that every tool in every fab runs exactly the same way.

After a fab successfully implements the new chip-making processes, engineers start investigating ways to improve transistor performance and the yield of working chips from each wafer. As soon as they can demonstrate an improvement, it is replicated at all other sites that make the same chips. Intel typically has three high-volume manufacturing fabs making our newest chips.

Linked by a wide-area network, these three fabs work together as one virtual factory, sharing the latest manufacturing process improvements and incorporating them in exactly the same fashion. Intel’s method of precisely copying processes across all our fabs has been occasionally derided by our competition to mean that we lack flexibility and agility. On the contrary, we believe it is an effective tool to manage changes continuously while reducing risk.

This ability to constantly tweak and replicate manufacturing procedures and recipes will become even more important as we push our chips down to smaller dimensions. The software will have to evolve, too. It will take advantage of a certain silicon ­symbiosis—the chips made by our software in turn run that software more efficiently. This is especially important considering that each new generation of chip creates hundreds more terabytes of engineering data that our Itanium- and Xeon-based servers will have to crunch.

We’ll need all the speed we can get. Smaller dimensions in next-generation nodes means more layers of wires and more daunting process challenges in making transistors, among other things. Despite the increasing difficulty, the time allowed for development—two years—won’t change. To hit the market ahead of our competition, we will have to run a highly adaptive technology development line, where we can do things like process different kinds of chips on individual wafers to get more data from fewer wafers faster.

Intel’s AMT provides a software framework that allows us to quickly add new functions and change existing modules. We don’t want to rewrite the whole system to accommodate each new generation of microprocessor. But we can add new code to existing applications as well as add or replace whole applications, depending on the circumstances. If we want to change the manufacturing flow to add steps or to change how wafers are routed through the line, we can implement those changes in our software quickly without having to recompile the code or test the entire system. Such flexibility is key to Intel’s ability to adapt to rapid changes in fabs within and between successive generations of chips.

Software has automated all routine tasks needed to run a fab. We don’t need people to stand in front of the tools to run the wafers or make the thousands of decisions that are required every day. That said, we will always need humans to enter our fabs to conduct routine maintenance on machines and to fix them when they break down. And, of course, we need humans—including the hundreds of Ph.D.s we have working on technology development—to create the procedures and chip recipes that will help us to continue to double the number of transistors per chip every couple of years. Software has freed our engineers to investigate ways to work with silicon through the 22-nm generation of chips. And we are looking forward to the day in the not-too-distant future when our software tests recipes for chips that might use carbon nanotubes as transistors and light-emitting semiconductors for optical interconnects.