Photo: Behzad Razavi/UCLA

DESIGN TRICKS : allow transceivers to accom­mo­date bulky components— for instance, by nesting square and octagonal induction coils one inside the other.

Some possible solutions are to transmit at very high power and to use adaptive-array antennas to send signals to their target by indirect routes, through reflection and refraction. It's better, though, to rely on lots of transceivers. If enough were strewn through an office—and even worn by the people who work there—any two devices would always be able to talk to each other directly or through a third node.

For this strategy to work, a transceiver must be made cheap enough, small enough, and frugal enough to run a long time on a small battery. These requirements are complicated by the 10-fold speedup in operating frequency. (Transistors have gotten faster, but not that much faster.) A major design overhaul will thus be needed. What's more, the connections between transistors have resistance, capacitance, and inductance, which tend to sap performance at these frequencies. And the high-speed, high-resolution, analog-to-digital and digital-to-analog converters needed to process gigabit-per-second data rates are real energy hogs.

The seriousness of these issues depends on just which integrated-circuit technology is used. Bipolar transistors made of silicon-germanium offer high speeds, and this technology makes it possible to fabricate high-quality passive devices, such as inductors, right on the chip, simplifying design and boosting performance. IBM has reported making 60-GHz silicon-germanium transceivers that can shoot data at 1 Gb/s for as far as 8 meters. But with multiple transceivers, analog-to-digital and digital-to-analog converters, and ever more complex signal processing, the cost of silicon-germanium becomes prohibitive.

CMOS chips are much less expensive, but the lower speed of the transistors and poorer quality of the passive devices make designing the circuits exceedingly tough. Nonetheless, the history of the semiconductor industry is littered with examples of products that were first built with bipolar technologies but were soon replaced with CMOS counterparts, suggesting that 60-GHz CMOS chips will in the end win out.

Designers clearly face high technical hurdles in fashioning CMOS circuits that can handle various RF-signal manipulations at 60 GHz. Many of these operations depend on heterodyning, in which the circuitry mixes two signals at different frequencies to produce an output that contains components at both the sum and the difference frequencies. A standard AM transmitter would, for example, multiply the relatively low-frequency audio signal to be broadcast (say, a 1-kilohertz tone) with the output of an oscillator running at a much higher radio frequency (say, 1000 kHz). The sum and difference of these two frequencies (999 kHz and 1001 kHz) fall just slightly above and below that of the RF oscillator. That's why the original audio signal is said to be “up-converted” to RF. The receiver for such an AM broadcast would typically use a similar oscillator to “down-convert” the RF signal back to audio, using exactly the same heterodyning principle.

For high-speed data communications at 60 GHz, such operations can be a nightmare to implement. For one thing, the oscillator would have to produce two 60-GHz outputs that are exactly 90 degrees out of phase. This is because the final modulated signal is produced by combining a sine and cosine. The generation and routing of these two phases, while maintaining a 90-degree difference between them, is hard at 60 GHz.

Also, controlling the precise frequency of a 60-GHz oscillator is tricky because it's running too fast to measure directly, as crystal-controlled frequency standards are limited to about 100 megahertz. The 60-GHz signal must first be fed into a frequency-divider circuit that reduces the frequency by a large factor (say, 600). Only then can the output be compared with a frequency standard, which indicates whether the rate of oscillation is faster or slower than desired, so that it can be corrected accordingly. The tactic is simple enough, but the limits on transistor speed make it difficult to fashion such frequency-divider circuits that work at 60 GHz.

Fortunately, with a little cunning, you can make a receiver work using a 40-GHz oscillator instead. The first step is to mix the output of the 40-GHz oscillator with the 60-GHz received signal. That operation down-converts the signal to the difference frequency: 20 GHz. To down-convert the signal the rest of the way, the receiver circuitry need not incorporate a separate 20-GHz oscillator; it can simply use the output of a divide-by-two frequency divider attached to its 40-GHz oscillator. Because it operates on 40 GHz rather than 60 GHz, such a frequency divider is comparatively easy to implement. What's more, it is less vexing to route signals around a chip at 40 GHz than at 60 GHz. And happily enough for designers, the transmission path can follow the receiver operations in the reverse order to avoid 60-GHz oscillators and frequency dividers. That is, the data stream to be transmitted is first up-converted to 20 GHz and only then raised to 60 GHz.

Using 40 GHz for the oscillator frequency is just one way to dodge some of the thorny problems posed by 60 GHz. The IBM transceiver takes a slightly different tack: it incorporates a 17-GHz oscillator followed by a frequency tripler to obtain 51 GHz, which is roughly 8.5 GHz below the target frequency. The 51 GHz thus can serve to down-convert the received signal to 8.5 GHz. And a divide-by-two frequency divider attached to the 17-GHz oscillator generates the 8.5 GHz needed for the second stage of down-conversion.