The Fastest, the Smallest, and the Strangest at IEDM

This year's IEEE International Electron Devices Meeting, as usual, is largely a race to the bottom

17 December 2008—At this year’s International Electron Devices Meeting (IEDM), in San Francisco, there are two big themes: One is the 22-nanometer CMOS technology node and how we’re going to get there; the other is what’s being called More Than Moore—the tricks and workarounds that designers will need to go beyond the kind of speed and density increases provided by Moore’s Law. Some tricks, like three-dimensional stacking and investigations into compound semiconductor materials, have been under development for a long time. But others are stranger than fiction, like a carbon phase-change memory that Qimonda is working on and MIT’s terahertz transistor. Here are a few developments that caught our eye.

PHOTO: MIT Microsystems Technology Laboratories

T-ray Terror: MIT engineers have devised a freaky-looking but record-setting device they say is optimized for a very high frequency of operation in analog and communications applications as well as in high-speed logic. Called an E-mode InAs PHEMTs (enhancement-mode indium arsenide p -type high-electron mobility transistor), it sets a record of more than 600 gigahertz for both f T (the maximum frequency at which the transistors provide a gain in current) and f max (the device’s maximum switching frequency). The 600 GHz measurement is well into the range of terahertz radiation, a difficult-to-get-to part of the spectrum that’s handy for seeing through clothing and identifying explosives at a distance. ”It is a very flexible technology with many possible applications at the leading edge,” says MIT’s Jesus del Alamo.

Bigger Bandwidth: Intel and Numonyx presented a silicon photonics chip capable of transmitting data at a rate of 200 gigabits per second. As microprocessor technology advances toward multicore and many-core architectures, optical interconnects are considered a promising way of getting data quickly in and out of chips. The ability to modulate an optical signal in a silicon chip has improved about a thousandfold in just the past five years, say Intel engineers. The company recently demonstrated a 40 Gb/s Si modulator. Intel and Numonyx got to 200 Gb/s by integrating eight such modulators with a wavelength demultiplexer and a wavelength multiplexer. As fast as that is, the Intel photonics group lost out to rival Luxtera for a US $44 million Defense Advanced Research Projects Agency award.


Mirror, Mirror on a Chip: With their micromirror array at 11 megapixels squeezed into 10 square centimeters, ASML and IMEC have made what they claim is the most dense and most reliable integrated micromirror array ever—about double the density of today’s state of the art. The array consists of 8 x 8 micrometer pixels that can be individually addressed by an analog voltage to tilt the micromirrors. Usually micromirrors are aluminum based, but aluminum suffers from reliability problems, so the devices require careful engineering. Replacing aluminum with silicon solves many of these problems, but integrating the silicon mirrors with the CMOS driving circuitry can usually be done only by bonding the micromirrors to the silicon wafer or die. Instead, the Benelux-based researchers built the mirrors [right and top of left] from polycrystalline silicon germanium. This material can be deposited at temperatures compatible with CMOS processing, allowing the silicon drive circuits [bottom left] to be built together with the micromirrors as one chip.

Smallest SRAM: How and whether the traditional on-chip microprocessor memory, 6-transistor SRAM will work at the 22-nanometer node and beyond are subjects of great debate. At IEDM 2008, AMD, Freescale, and IBM demonstrated a 22-nm-node, fully functional 0.1 m2 6T-SRAM cell, the world’s smallest by 37 percent. To enable the technology to advance, the presenters used so-called band edge high- k dielectric and metal gate stacks, transistors with 25-nm gate lengths, and other new tricks.

PHOTO: Qimonda

Smallest DRAM: Qimonda engineers have presented data on the smallest DRAM cell yet, having a footprint of just 0.013m2. DRAM makers have been lowering the voltage in their chips in an effort to save power. An architecture called buried wordline, in which an interconnect is buried inside the chip’s silicon, is facilitating this by reducing power-sapping capacitances in the chip.

Carbon Memories: Qimonda compared three types of carbon, namely carbon nanotubes, graphenelike conductive carbon, and insulating carbon, for use as resistance-changing material in a new kind of high-density nonvolatile memory. They found that it was possible to switch from a low-conductivity state [left] to a high-conductivity state [right] and vice versa by applying appropriate current pulses to the carbon element. The conductive state would then represent 1 bit in memory. In contrast to other switchable memory materials, carbon could be scalable to very small feature sizes, according to Qimonda engineers.


Why Phi?: Though last year’s IEDM theme was multigate transistors, the enthusiasm has petered out a bit this year. This multigate transistor is the exception: France’s CEA-LETI developed the 3-D device, which has features smaller than 15 nm. They dubbed it the Phi-gate transistor because the shape created by its nanowire channel and gates supposedly resembles the Greek letter phi (). You’ll have to trust them on that one; we don’t see it.

Multigate transistors may no longer be a buzzword, but the motivation to develop them hasn’t gone away: As transistors get smaller, current leakage will become worse. One potential solution is to restrict the current to flowing through a nanowire channel (or in this case, stacks of nanowires) and partially or completely surrounding the channel with gates for maximum control.

The FET’s nanowire stacks are built by starting with alternating layers of silicon and silicon germanium. After etching away the SiGe, the French researchers were left with a stack of horizontal silicon nanowires. They then fabricated gates around each individual nanowire and compared their 3-D FET to similarly sized transistors. Their results showed better on- and off-current performance and, they claim, better potential for scaling to smaller dimensions.